OTBN Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: `d7d3545`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	43.283us	1	1	100.00
V1	single_binary	otbn_single	13.000s	114.192us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	20.988us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	106.822us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	28.396us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	19.393us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	35.481us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	106.822us	1	1	100.00
		otbn_csr_aliasing	7.000s	19.393us	1	1	100.00
V1	mem_walk	otbn_mem_walk	16.000s	1.217ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	14.000s	130.192us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	14.000s	106.001us	1	1	100.00
V2	multi_error	otbn_multi_err	37.849s		0	1	0.00
V2	back_to_back	otbn_multi	25.000s	108.584us	1	1	100.00
V2	stress_all	otbn_stress_all	18.000s	139.317us	1	1	100.00
V2	lc_escalation	otbn_escalate	13.000s	61.272us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	28.232us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	8.000s	55.536us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	53.926us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	14.842us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	95.652us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	95.652us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	20.988us	1	1	100.00
		otbn_csr_rw	6.000s	106.822us	1	1	100.00
		otbn_csr_aliasing	7.000s	19.393us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	44.753us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	20.988us	1	1	100.00
		otbn_csr_rw	6.000s	106.822us	1	1	100.00
		otbn_csr_aliasing	7.000s	19.393us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	44.753us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	mem_integrity	otbn_imem_err	10.000s	35.044us	1	1	100.00
		otbn_dmem_err	9.000s	39.076us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	106.254us	1	1	100.00
		otbn_controller_ispr_rdata_err	45.000s	221.930us	1	1	100.00
		otbn_mac_bignum_acc_err	21.000s	60.947us	1	1	100.00
		otbn_urnd_err	7.000s	9.789us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	27.443us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	33.529us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	32.825us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
		otbn_tl_intg_err	17.000s	111.455us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	21.000s	173.045us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	43.283us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	39.076us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	35.044us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	17.000s	111.455us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	13.000s	61.272us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	35.044us	1	1	100.00
		otbn_dmem_err	9.000s	39.076us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	28.232us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	27.443us	1	1	100.00
		otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	13.000s	114.192us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	35.044us	1	1	100.00
		otbn_dmem_err	9.000s	39.076us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	28.232us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	27.443us	1	1	100.00
		otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	13.000s	61.272us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	35.044us	1	1	100.00
		otbn_dmem_err	9.000s	39.076us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	28.232us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	27.443us	1	1	100.00
		otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	13.000s	114.192us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	13.285us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	130.833us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	16.000s	51.601us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	16.000s	51.601us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	8.000s	37.604us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	8.000s	651.849us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	11.560us	0	1	0.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	11.560us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	41.229us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	13.000s	114.192us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	13.000s	114.192us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	13.000s	114.192us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	25.000s	108.584us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	13.000s	114.192us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	13.000s	114.192us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	8.000s	20.491us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	13.000s	114.192us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.450m	2.584ms	1	1	100.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.250m	2.194ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	41	90.24

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_sec_wipe_err has 1 failures.

0.otbn_sec_wipe_err.111274245798298144224305372742884865646681210203497706985808793984540189207299
Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 41229299 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  41229299 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  41229299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_stack_addr_integ_chk has 1 failures.

0.otbn_stack_addr_integ_chk.62560969359689794810631032108694679660145468428124567018110828478409215885031
Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 11559506 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  11559506 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  11559506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job returned non-zero exit code has 1 failures:

Test otbn_multi_err has 1 failures.

0.otbn_multi_err.11764767875073396527720939049440507182045632974084003076331307074904849409699
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log

  make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --src-dir /nightly/runs/opentitan/hw/ip/otbn/dv/otbnsim/test/simple/multi /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_multi_err.3351799459 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_multi_err.3351799459 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=3351799459 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_sequential_vseq -nowarn DSEM2009' seed=11764767875073396527720939049440507182045632974084003076331307074904849409699 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_sequential_vseq

  [make]: pre_run
  mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest
  cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --src-dir /nightly/runs/opentitan/hw/ip/otbn/dv/otbnsim/test/simple/multi /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/otbn-binaries
  ~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest
  2025/05/21 18:52:34 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
  Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
  FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.1397663026986682928750275445531110235059624483013044992941511048391212671432
    Line 216, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2194427205 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2194427205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```