PATTGEN Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: `d7d3545`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	5.000s	37.496us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	29.863us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	34.529us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	68.367us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	20.066us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	17.352us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	34.529us	1	1	100.00
		pattgen_csr_aliasing	4.000s	20.066us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	2.883m	69.739ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	24.000s	802.515us	1	1	100.00
V2	error	pattgen_error	4.000s	54.207us	1	1	100.00
V2	stress_all	pattgen_stress_all	3.483m	24.948ms	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	13.922us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	14.284us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	119.037us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	119.037us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	29.863us	1	1	100.00
		pattgen_csr_rw	4.000s	34.529us	1	1	100.00
		pattgen_csr_aliasing	4.000s	20.066us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	33.720us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	29.863us	1	1	100.00
		pattgen_csr_rw	4.000s	34.529us	1	1	100.00
		pattgen_csr_aliasing	4.000s	20.066us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	33.720us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	102.573us	1	1	100.00
		pattgen_sec_cm	4.000s	48.785us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	102.573us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	21.000s	2.159ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	19.000s	10.034ms	0	1	0.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 0.pattgen_inactive_level.24810065551345201544771897234398421713327733358344884289292863515978183514267
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10033507712 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x105dcf10, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10033507712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.82676962346303662888360118308909244307499096259429953153448500373927768740651
Line 118, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 446919418 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 446929728 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 446929728 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 447002647 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.10539850473026741979438812945764017687975813429066556446173319101986035043328
    Line 136, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 24948044613 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ----------------------------------------
  Name         Type          Size   Value
  ----------------------------------------
  exp_item     pattgen_item  -      @11457
```