ROM_CTRL/32KB Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.920s 178.497us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.280s 534.269us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.910s 175.381us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.330s 123.742us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.500s 312.822us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.180s 402.194us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.910s 175.381us 1 1 100.00
rom_ctrl_csr_aliasing 4.500s 312.822us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.510s 127.460us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.410s 131.186us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.430s 401.361us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.760s 2.161ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.190s 560.037us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.320s 127.043us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.470s 169.524us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.470s 169.524us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.280s 534.269us 1 1 100.00
rom_ctrl_csr_rw 4.910s 175.381us 1 1 100.00
rom_ctrl_csr_aliasing 4.500s 312.822us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.980s 1.087ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.280s 534.269us 1 1 100.00
rom_ctrl_csr_rw 4.910s 175.381us 1 1 100.00
rom_ctrl_csr_aliasing 4.500s 312.822us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.980s 1.087ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 35.610s 3.402ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 14.100s 757.071us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.974m 2.199ms 1 1 100.00
rom_ctrl_tl_intg_err 42.660s 312.201us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.974m 2.199ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.974m 2.199ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 35.610s 3.402ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 35.610s 3.402ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 35.610s 3.402ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 35.610s 3.402ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 35.610s 3.402ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.974m 2.199ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.974m 2.199ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.920s 178.497us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.920s 178.497us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.920s 178.497us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 42.660s 312.201us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 35.610s 3.402ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.190s 560.037us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 35.610s 3.402ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 35.610s 3.402ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 35.610s 3.402ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 14.100s 757.071us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.974m 2.199ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 23.240s 1.731ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00