ROM_CTRL/64KB Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.800s 814.431us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.010s 1.148ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.690s 554.455us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.110s 242.031us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.040s 699.356us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.660s 395.298us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.690s 554.455us 1 1 100.00
rom_ctrl_csr_aliasing 6.040s 699.356us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.750s 294.768us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.650s 3.561ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.910s 712.029us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 37.940s 16.462ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.970s 725.775us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 8.930s 3.660ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.750s 289.358us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.750s 289.358us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.010s 1.148ms 1 1 100.00
rom_ctrl_csr_rw 6.690s 554.455us 1 1 100.00
rom_ctrl_csr_aliasing 6.040s 699.356us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.130s 314.600us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.010s 1.148ms 1 1 100.00
rom_ctrl_csr_rw 6.690s 554.455us 1 1 100.00
rom_ctrl_csr_aliasing 6.040s 699.356us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.130s 314.600us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.128m 13.536ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 36.160s 11.748ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.029m 666.687us 1 1 100.00
rom_ctrl_tl_intg_err 1.109m 1.611ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.029m 666.687us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.029m 666.687us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.128m 13.536ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.128m 13.536ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.128m 13.536ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.128m 13.536ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.128m 13.536ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.029m 666.687us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.029m 666.687us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.800s 814.431us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.800s 814.431us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.800s 814.431us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.109m 1.611ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.128m 13.536ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.970s 725.775us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.128m 13.536ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.128m 13.536ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.128m 13.536ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 36.160s 11.748ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.029m 666.687us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.617m 4.246ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00