RV_TIMER Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.590s	29.970us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.840s	32.064us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.640s	47.833us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.690s	542.901us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.680s	58.742us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.760s	28.219us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.640s	47.833us	1	1	100.00
		rv_timer_csr_aliasing	1.680s	58.742us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	2.370s	380.257us	1	1	100.00
V2	disabled	rv_timer_disabled	2.030s	523.813us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	7.159m	654.587ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	7.159m	654.587ms	1	1	100.00
V2	stress	rv_timer_stress_all	3.880s	4.717ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.450s	11.997us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.490s	34.778us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.490s	171.365us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.490s	171.365us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.840s	32.064us	1	1	100.00
		rv_timer_csr_rw	1.640s	47.833us	1	1	100.00
		rv_timer_csr_aliasing	1.680s	58.742us	1	1	100.00
		rv_timer_same_csr_outstanding	1.880s	24.646us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.840s	32.064us	1	1	100.00
		rv_timer_csr_rw	1.640s	47.833us	1	1	100.00
		rv_timer_csr_aliasing	1.680s	58.742us	1	1	100.00
		rv_timer_same_csr_outstanding	1.880s	24.646us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.010s	374.808us	1	1	100.00
		rv_timer_tl_intg_err	1.950s	351.417us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.950s	351.417us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	18.410s	4.458ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.570s	22.241us	1	1	100.00
		rv_timer_max	1.470s	18.628us	1	1	100.00
		TOTAL			19	19	100.00