SPI_DEVICE/1R1W Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.296m	141.092ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.910s	26.221us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.200s	56.288us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.590s	3.621ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.710s	2.068ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.490s	66.074us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.200s	56.288us	1	1	100.00
		spi_device_csr_aliasing	14.710s	2.068ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.770s	11.617us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.480s	201.274us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.660s	13.442us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.620s	1.157us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.580s	3.465us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.680s	159.068us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	4.680s	159.068us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.700s	3.806ms	1	1	100.00
		spi_device_tpm_sts_read	1.750s	240.120us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	11.090s	29.530ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	7.500s	2.413ms	1	1	100.00
		spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.900s	13.520ms	1	1	100.00
		spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.900s	13.520ms	1	1	100.00
		spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.410s	835.580us	1	1	100.00
		spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.410s	835.580us	1	1	100.00
		spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.410s	835.580us	1	1	100.00
		spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.410s	835.580us	1	1	100.00
		spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.410s	835.580us	1	1	100.00
		spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	10.370s	3.849ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	12.050s	14.932ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	12.050s	14.932ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	12.050s	14.932ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	8.560s	831.333us	1	1	100.00
		spi_device_read_buffer_direct	7.890s	1.232ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	12.050s	14.932ms	1	1	100.00
		spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.085m	23.446ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.770s	1.740ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.770s	1.740ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.296m	141.092ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	25.030s	5.357ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.924m	112.859ms	1	1	100.00
V2	alert_test	spi_device_alert_test	2.110s	14.682us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.830s	47.774us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.340s	73.563us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.340s	73.563us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.910s	26.221us	1	1	100.00
		spi_device_csr_rw	2.200s	56.288us	1	1	100.00
		spi_device_csr_aliasing	14.710s	2.068ms	1	1	100.00
		spi_device_same_csr_outstanding	3.210s	395.218us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.910s	26.221us	1	1	100.00
		spi_device_csr_rw	2.200s	56.288us	1	1	100.00
		spi_device_csr_aliasing	14.710s	2.068ms	1	1	100.00
		spi_device_same_csr_outstanding	3.210s	395.218us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.800s	38.195us	1	1	100.00
		spi_device_tl_intg_err	14.960s	2.068ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.960s	2.068ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.630s	24.584us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.47743631520253100811725893964961718900224996719367861665738435395631495475526
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    974722 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[65])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    974722 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    974722 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[961])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.97629685427112439381014822735189615229428088231986817707299831310796667208620
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    922668 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2e2a2a [1011100010101000101010] vs 0x0 [0])
        UVM_ERROR @    963668 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9e17da [100111100001011111011010] vs 0x0 [0])
        UVM_ERROR @   1014668 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9d8e45 [100111011000111001000101] vs 0x0 [0])
        UVM_ERROR @   1110668 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x51e6df [10100011110011011011111] vs 0x0 [0])
        UVM_ERROR @   1204668 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa0e140 [101000001110000101000000] vs 0x0 [0])