SPI_DEVICE/2P Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 1.352m 29.404ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.920s 170.362us 1 1 100.00
V1 csr_rw spi_device_csr_rw 2.550s 275.646us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 10.630s 9.049ms 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 16.620s 11.295ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.510s 847.772us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.550s 275.646us 1 1 100.00
spi_device_csr_aliasing 16.620s 11.295ms 1 1 100.00
V1 mem_walk spi_device_mem_walk 1.560s 14.366us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.660s 131.222us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 1.620s 25.523us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.730s 258.628us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 1.540s 15.957us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 2.030s 77.411us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 2.030s 77.411us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 3.900s 2.131ms 1 1 100.00
spi_device_tpm_sts_read 1.810s 33.458us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 19.840s 11.696ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 2.670s 404.925us 1 1 100.00
spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 5.490s 4.247ms 1 1 100.00
spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 5.490s 4.247ms 1 1 100.00
spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 4.480s 546.175us 1 1 100.00
spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 4.480s 546.175us 1 1 100.00
spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 4.480s 546.175us 1 1 100.00
spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 4.480s 546.175us 1 1 100.00
spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 4.480s 546.175us 1 1 100.00
spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 20.080s 34.757ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 4.750s 4.017ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 4.750s 4.017ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 4.750s 4.017ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 6.490s 1.127ms 1 1 100.00
spi_device_read_buffer_direct 5.390s 3.069ms 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 4.750s 4.017ms 1 1 100.00
spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 quad_spi spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 dual_spi spi_device_flash_all 1.043m 37.396ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 2.680s 110.532us 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 2.680s 110.532us 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 1.352m 29.404ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 40.850s 17.701ms 1 1 100.00
V2 stress_all spi_device_stress_all 5.000m 1.165s 1 1 100.00
V2 alert_test spi_device_alert_test 1.550s 75.538us 1 1 100.00
V2 intr_test spi_device_intr_test 1.690s 44.610us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 4.150s 1.229ms 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 4.150s 1.229ms 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.920s 170.362us 1 1 100.00
spi_device_csr_rw 2.550s 275.646us 1 1 100.00
spi_device_csr_aliasing 16.620s 11.295ms 1 1 100.00
spi_device_same_csr_outstanding 3.120s 150.795us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.920s 170.362us 1 1 100.00
spi_device_csr_rw 2.550s 275.646us 1 1 100.00
spi_device_csr_aliasing 16.620s 11.295ms 1 1 100.00
spi_device_same_csr_outstanding 3.120s 150.795us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 2.220s 103.537us 1 1 100.00
spi_device_tl_intg_err 6.340s 662.609us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 6.340s 662.609us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 3.112m 186.762ms 1 1 100.00
TOTAL 33 33 100.00