SPI_HOST Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	36.000s	4.510ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	29.864us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	74.507us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	611.511us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	32.374us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	110.206us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	74.507us	1	1	100.00
		spi_host_csr_aliasing	5.000s	32.374us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	42.223us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	17.149us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	9.000s	23.792us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	9.000s	77.022us	1	1	100.00
		spi_host_error_cmd	9.000s	15.539us	1	1	100.00
		spi_host_event	9.967m	85.108ms	1	1	100.00
V2	clock_rate	spi_host_speed	29.000s	10.043ms	0	1	0.00
V2	speed	spi_host_speed	29.000s	10.043ms	0	1	0.00
V2	chip_select_timing	spi_host_speed	29.000s	10.043ms	0	1	0.00
V2	sw_reset	spi_host_sw_reset	10.000s	86.780us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	7.000s	34.056us	1	1	100.00
V2	cpol_cpha	spi_host_speed	29.000s	10.043ms	0	1	0.00
V2	full_cycle	spi_host_speed	29.000s	10.043ms	0	1	0.00
V2	duplex	spi_host_smoke	36.000s	4.510ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	36.000s	4.510ms	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	88.774us	1	1	100.00
V2	spien	spi_host_spien	11.000s	385.064us	1	1	100.00
V2	stall	spi_host_status_stall	1.667m	34.783ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	186.621us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	9.000s	77.022us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	15.943us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	38.505us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	55.548us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	55.548us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	29.864us	1	1	100.00
		spi_host_csr_rw	4.000s	74.507us	1	1	100.00
		spi_host_csr_aliasing	5.000s	32.374us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	61.757us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	29.864us	1	1	100.00
		spi_host_csr_rw	4.000s	74.507us	1	1	100.00
		spi_host_csr_aliasing	5.000s	32.374us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	61.757us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	102.429us	1	1	100.00
		spi_host_sec_cm	4.000s	67.060us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	102.429us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.967m	10.141ms	1	1	100.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:234) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
  • Test spi_host_speed has 1 failures.

    • 0.spi_host_speed.4356115607701313648000435233277502547029805866684149690664956531937519254119
      Line 291, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log

        UVM_FATAL @ 10042534758 ps: (spi_host_base_vseq.sv:234) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x52c23194, Comparison=CompareOpEq, exp_data=0x0, call_count=54
        UVM_INFO @ 10042534758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---