SRAM_CTRL/MAIN Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	18.270s	9.751ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.620s	69.140us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.720s	22.911us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.990s	47.960us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.700s	14.974us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.320s	729.425us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.720s	22.911us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	14.974us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.403m	147.854ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.127m	22.265ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.790m	11.298ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.414m	5.683ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	8.164m	39.638ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	15.281m	95.692ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	22.490s	20.277ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.748m	12.813ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	3.750s	740.661us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.688m	6.764ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	28.780s	756.985us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.630s	1.462ms	1	1	100.00
		sram_ctrl_throughput_w_readback	6.940s	3.438ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.962m	7.685ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.150s	358.730us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	43.485m	74.523ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.990s	25.617us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.940s	132.972us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.940s	132.972us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.620s	69.140us	1	1	100.00
		sram_ctrl_csr_rw	1.720s	22.911us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	14.974us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	15.777us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.620s	69.140us	1	1	100.00
		sram_ctrl_csr_rw	1.720s	22.911us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	14.974us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	15.777us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	34.860s	24.315ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.640s	12.082us	0	1	0.00
		sram_ctrl_tl_intg_err	2.200s	325.214us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.640s	12.082us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.200s	325.214us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.962m	7.685ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.962m	7.685ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.720s	22.911us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.748m	12.813ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.748m	12.813ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.748m	12.813ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	22.490s	20.277ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.020s	1.801ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	34.860s	24.315ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.220s	711.773us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	18.270s	9.751ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	18.270s	9.751ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.748m	12.813ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.640s	12.082us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	22.490s	20.277ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.640s	12.082us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.640s	12.082us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	18.270s	9.751ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.640s	12.082us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	26.280s	2.538ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.58503752133892746705914482255158787421518905093916021490260521147218854673878
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12082009 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12082009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---