SRAM_CTRL/RET Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.040s	484.353us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.110s	25.835us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.980s	25.349us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.270s	182.193us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.730s	35.227us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.750s	32.894us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.980s	25.349us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	35.227us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.310s	208.874us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.080s	409.137us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.618m	22.446ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.943m	8.175ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	44.210s	3.929ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.782m	1.062ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.780s	2.655ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.690m	7.104ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	28.180s	2.033ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.383m	10.412ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	12.750s	328.217us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	12.260s	100.597us	1	1	100.00
		sram_ctrl_throughput_w_readback	23.370s	203.929us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.119m	22.333ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.790s	209.162us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	11.686m	33.550ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.570s	46.202us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.170s	33.567us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.170s	33.567us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.110s	25.835us	1	1	100.00
		sram_ctrl_csr_rw	1.980s	25.349us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	35.227us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	18.726us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.110s	25.835us	1	1	100.00
		sram_ctrl_csr_rw	1.980s	25.349us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	35.227us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	18.726us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.280s	3.525ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.520s	18.203us	0	1	0.00
		sram_ctrl_tl_intg_err	2.310s	445.162us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.520s	18.203us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.310s	445.162us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.119m	22.333ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.119m	22.333ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.980s	25.349us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.690m	7.104ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.690m	7.104ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.690m	7.104ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.780s	2.655ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.550s	124.782us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.280s	3.525ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.670s	35.544us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.040s	484.353us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.040s	484.353us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.690m	7.104ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.520s	18.203us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.780s	2.655ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.520s	18.203us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.520s	18.203us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.040s	484.353us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.520s	18.203us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.415m	1.367ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.18069201778839277845365687517493310124264394384564351392170849003681589045409
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 124781678 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 124781678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.103561499205514370950342292408423153068079710503600588679981970304922695126863
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  18202661 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  18202661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---