SYSRST_CTRL Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	2.830s	2.133ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	3.010s	2.504ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.270s	2.402ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.320s	2.332ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	7.490s	6.023ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	5.260s	2.036ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	59.500s	37.803ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.980s	3.175ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.310s	2.040ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	5.260s	2.036ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.980s	3.175ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	47.120s	48.224ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	37.660s	86.600ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	8.290s	3.373ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	2.690s	2.790ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	6.410s	2.510ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	5.230s	2.114ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	2.660s	4.444ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	6.170s	2.608ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	5.840s	4.660ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	19.690s	39.488ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	45.790s	186.327ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	2.400s	2.038ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	2.750s	2.035ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.760s	2.458ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.760s	2.458ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	7.490s	6.023ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.260s	2.036ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.980s	3.175ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	11.110s	10.260ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	7.490s	6.023ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.260s	2.036ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.980s	3.175ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	11.110s	10.260ms	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	sysrst_ctrl_sec_cm	41.590s	22.010ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	7.100s	22.428ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	7.100s	22.428ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	8.870s	13.392ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:115) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (* [*] vs * [*]) has 1 failures:
  • Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.sysrst_ctrl_stress_all_with_rand_reset.77227526131848825851706549022624687789916383219444974335461820437287516145677
      Line 405, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8701653670 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 8705161551 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
        Stress w/ reset is done for run 3/10
        UVM_INFO @ 8708757448 ps: (cip_base_vseq.sv:787) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 4/10
        UVM_INFO @ 8708757448 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/123