UART Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	3.170s	689.771us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.480s	39.818us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.730s	44.639us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.300s	192.567us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.560s	39.067us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.780s	44.440us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.730s	44.639us	1	1	100.00
		uart_csr_aliasing	1.560s	39.067us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.860s	234.787us	1	1	100.00
V2	parity	uart_smoke	3.170s	689.771us	1	1	100.00
		uart_tx_rx	1.860s	234.787us	1	1	100.00
V2	parity_error	uart_intr	4.990s	20.489ms	1	1	100.00
		uart_rx_parity_err	21.690s	32.250ms	1	1	100.00
V2	watermark	uart_tx_rx	1.860s	234.787us	1	1	100.00
		uart_intr	4.990s	20.489ms	1	1	100.00
V2	fifo_full	uart_fifo_full	9.800s	127.963ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	49.910s	41.283ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.773m	97.087ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.990s	20.489ms	1	1	100.00
V2	rx_break_err	uart_intr	4.990s	20.489ms	1	1	100.00
V2	rx_timeout	uart_intr	4.990s	20.489ms	1	1	100.00
V2	perf	uart_perf	11.559m	17.694ms	1	1	100.00
V2	sys_loopback	uart_loopback	7.170s	3.962ms	1	1	100.00
V2	line_loopback	uart_loopback	7.170s	3.962ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	13.960s	21.071ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.170s	3.437ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	11.480s	7.319ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	40.480s	6.071ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.240m	119.579ms	1	1	100.00
V2	stress_all	uart_stress_all	9.757m	411.568ms	1	1	100.00
V2	alert_test	uart_alert_test	1.660s	23.909us	1	1	100.00
V2	intr_test	uart_intr_test	1.450s	25.225us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.830s	157.488us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.830s	157.488us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.480s	39.818us	1	1	100.00
		uart_csr_rw	1.730s	44.639us	1	1	100.00
		uart_csr_aliasing	1.560s	39.067us	1	1	100.00
		uart_same_csr_outstanding	1.580s	85.378us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.480s	39.818us	1	1	100.00
		uart_csr_rw	1.730s	44.639us	1	1	100.00
		uart_csr_aliasing	1.560s	39.067us	1	1	100.00
		uart_same_csr_outstanding	1.580s	85.378us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	2.330s	55.684us	1	1	100.00
		uart_tl_intg_err	1.850s	60.010us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.850s	60.010us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	19.870s	10.712ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00