CHIP Simulation Results

Wednesday May 21 2025 18:35:43 UTC

GitHub Revision: `d7d3545`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.522m	2.842ms	1	1	100.00
		chip_sw_example_rom	1.187m	1.880ms	1	1	100.00
		chip_sw_example_manufacturer	1.882m	3.079ms	1	1	100.00
		chip_sw_example_concurrency	2.208m	2.936ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.456m	4.834ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.499m	5.206ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.807m	3.499ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	57.786m	33.361ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	8.477m	10.345ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	57.786m	33.361ms	1	1	100.00
		chip_csr_rw	5.499m	5.206ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.950s	184.075us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.889m	4.158ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.889m	4.158ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.889m	4.158ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	7.043m	5.143ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	7.043m	5.143ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.043m	4.316ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.742m	3.957ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.692m	4.348ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	26.584m	13.166ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.385m	8.542ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.119m	3.654ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.413m	4.984ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.413m	4.984ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.539m	3.461ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.669m	3.576ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.080m	3.517ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.533m	3.189ms	1	1	100.00
		chip_tap_straps_testunlock0	4.194m	5.419ms	1	1	100.00
		chip_tap_straps_rma	3.885m	4.740ms	1	1	100.00
		chip_tap_straps_prod	1.616m	2.459ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.979m	2.936ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.910m	9.322ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.013m	6.206ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.013m	6.206ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.159m	7.766ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	27.407m	17.786ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.367m	4.225ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.065m	6.097ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.049m	17.793ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.164m	3.469ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.210m	6.104ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.593m	2.370ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	21.430m	11.610ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.215m	3.377ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.227m	4.444ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.067m	3.038ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.626m	2.993ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	3.845m	4.674ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.435m	5.141ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.303m	2.636ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.435m	5.141ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.002m	2.481ms	1	1	100.00
		chip_sw_aes_smoketest	2.731m	2.818ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.145m	3.594ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.576m	2.457ms	1	1	100.00
		chip_sw_csrng_smoketest	3.151m	3.550ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.644m	3.138ms	1	1	100.00
		chip_sw_gpio_smoketest	2.860m	2.956ms	1	1	100.00
		chip_sw_hmac_smoketest	2.562m	2.882ms	1	1	100.00
		chip_sw_kmac_smoketest	2.905m	3.595ms	1	1	100.00
		chip_sw_otbn_smoketest	12.352m	7.655ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.069m	4.892ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.939m	6.302ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.150m	3.183ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.185m	2.672ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.902m	2.643ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.660m	3.061ms	1	1	100.00
		chip_sw_uart_smoketest	2.495m	3.520ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.894m	2.977ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.862m	5.527ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.009h	60.470ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.798m	14.535ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.246m	4.644ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.461m	3.243ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.036m	2.683ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.764h	54.102ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.913h	57.497ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	59.630s	2.443ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	59.630s	2.443ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	57.786m	33.361ms	1	1	100.00
		chip_same_csr_outstanding	15.890m	16.864ms	1	1	100.00
		chip_csr_hw_reset	2.456m	4.834ms	1	1	100.00
		chip_csr_rw	5.499m	5.206ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	57.786m	33.361ms	1	1	100.00
		chip_same_csr_outstanding	15.890m	16.864ms	1	1	100.00
		chip_csr_hw_reset	2.456m	4.834ms	1	1	100.00
		chip_csr_rw	5.499m	5.206ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	42.630s	2.338ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.000s	51.953us	1	1	100.00
		xbar_smoke_large_delays	1.026m	10.358ms	1	1	100.00
		xbar_smoke_slow_rsp	49.450s	5.882ms	1	1	100.00
		xbar_random_zero_delays	7.390s	110.544us	1	1	100.00
		xbar_random_large_delays	56.860s	9.757ms	1	1	100.00
		xbar_random_slow_rsp	4.203m	30.764ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	14.760s	578.464us	1	1	100.00
		xbar_error_and_unmapped_addr	4.680s	66.875us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	19.820s	441.950us	1	1	100.00
		xbar_error_and_unmapped_addr	4.680s	66.875us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	56.290s	2.847ms	1	1	100.00
		xbar_access_same_device_slow_rsp	6.125m	42.925ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	8.550s	121.051us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	4.069m	12.744ms	1	1	100.00
		xbar_stress_all_with_error	1.170m	1.513ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	28.110s	147.651us	1	1	100.00
		xbar_stress_all_with_reset_error	51.640s	257.697us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.798m	14.535ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	35.468m	26.854ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.758m	15.288ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.663m	10.850ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.293m	15.382ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.501m	15.705ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.701m	15.645ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.898m	14.975ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	34.990s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	27.930s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.580s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	26.910s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	29.690s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	33.650s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	28.020s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	30.530s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	28.250s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.090s	10.120us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	27.450s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	27.180s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.600s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.240s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.870s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	28.210s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.480s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.430s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.600s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.230s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.020s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.480s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.780s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	29.680s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	27.500s	10.160us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.831m	10.772ms	1	1	100.00
		rom_e2e_asm_init_dev	36.201m	15.187ms	1	1	100.00
		rom_e2e_asm_init_prod	38.330m	15.311ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.480m	15.391ms	1	1	100.00
		rom_e2e_asm_init_rma	37.628m	15.577ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.410m	14.486ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.229m	14.798ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.290m	14.951ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.289m	15.938ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.236m	35.249ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.236m	35.249ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.333m	2.895ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.164m	3.469ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.466m	2.898ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.661m	2.853ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	12.223m	6.953ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.261m	2.515ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	3.822m	4.986ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.634m	5.938ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.513m	5.880ms	1	1	100.00
		chip_plic_all_irqs_10	4.398m	2.917ms	1	1	100.00
		chip_plic_all_irqs_20	6.091m	3.832ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.283m	2.861ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.526m	11.823ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.464m	3.376ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.627m	3.246ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.415m	12.157ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.573m	8.998ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.582m	9.152ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.575m	7.446ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.237h	256.299ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.058m	4.162ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.069m	4.892ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.058m	4.162ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.974m	9.437ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.974m	9.437ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.870m	6.743ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.006m	5.034ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.473m	6.206ms	1	1	100.00
		chip_sw_aes_idle	2.661m	2.853ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.916m	2.855ms	1	1	100.00
		chip_sw_kmac_idle	1.890m	2.638ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.093m	4.379ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.412m	4.501ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.931m	4.779ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.093m	4.418ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.200m	8.960ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.310m	3.901ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.947m	4.112ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.854m	4.516ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.801m	5.116ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.332m	3.551ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.578m	4.176ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.159m	7.766ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	9.148m	10.007ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.854m	4.516ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.801m	5.116ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.367m	4.225ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.065m	6.097ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.049m	17.793ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.164m	3.469ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.210m	6.104ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.593m	2.370ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	21.430m	11.610ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.215m	3.377ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.227m	4.444ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.067m	3.038ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.981m	3.006ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.556m	4.237ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.686m	7.989ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	48.235m	24.260ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.533m	2.977ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.473m	2.579ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	19.268m	13.010ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.479m	2.629ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.043m	4.293ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.840m	23.585ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.801h	128.951ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.159m	7.766ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.320m	4.501ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.231m	3.204ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.634m	5.938ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	18.573m	8.998ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	18.321m	8.420ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.872m	2.807ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.211m	6.747ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.746m	2.497ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	47.745m	18.308ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.614m	3.341ms	1	1	100.00
		chip_sw_edn_entropy_reqs	13.590m	6.472ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.614m	3.341ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	18.321m	8.420ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.939m	2.552ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.254m	23.349ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.700m	5.113ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.065m	6.097ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.249m	3.788ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.367m	4.225ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	55.911m	43.676ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.254m	23.349ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.932m	3.169ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	14.230m	7.720ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.938m	4.772ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	55.911m	43.676ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.938m	4.772ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.938m	4.772ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.938m	4.772ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.938m	4.772ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.634m	5.938ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.301m	8.384ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.168m	5.091ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.976m	5.318ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.976m	5.318ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.601m	3.350ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.593m	2.370ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.916m	2.855ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.786m	3.247ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	6.220m	3.985ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.003m	4.954ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.601m	4.906ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.311m	5.152ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.598m	3.517ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	14.230m	7.720ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	21.430m	11.610ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	27.835m	13.882ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	12.223m	6.953ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	37.674m	12.832ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.462m	2.712ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.616m	3.129ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.215m	3.377ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	14.230m	7.720ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.833m	5.304ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.339m	2.699ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	13.609m	6.208ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.890m	2.638ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	3.822m	4.986ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.533m	3.189ms	1	1	100.00
		chip_tap_straps_rma	3.885m	4.740ms	1	1	100.00
		chip_tap_straps_prod	1.616m	2.459ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.960m	3.007ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.833m	5.304ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.833m	5.304ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.833m	5.304ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	28.285m	12.774ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.938m	4.772ms	1	1	100.00
		chip_sw_flash_rma_unlocked	55.911m	43.676ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.310m	3.475ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.327m	5.001ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.311m	6.103ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.705m	7.098ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.833m	5.304ms	1	1	100.00
		chip_sw_keymgr_key_derivation	14.230m	7.720ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.171m	10.070ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.020m	7.662ms	1	1	100.00
		chip_prim_tl_access	4.301m	8.384ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	9.148m	10.007ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.310m	3.901ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.947m	4.112ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.854m	4.516ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.801m	5.116ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.332m	3.551ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.578m	4.176ms	1	1	100.00
		chip_tap_straps_dev	1.533m	3.189ms	1	1	100.00
		chip_tap_straps_rma	3.885m	4.740ms	1	1	100.00
		chip_tap_straps_prod	1.616m	2.459ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.448m	11.952ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.616m	2.698ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.788m	3.916ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.381m	3.183ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.834m	3.199ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	24.563m	32.880ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.448m	11.952ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.051h	48.284ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	58.231m	48.921ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.708m	8.818ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	58.653m	46.210ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	24.563m	32.880ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.432m	3.081ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.241m	3.171ms	1	1	100.00
		rom_volatile_raw_unlock	1.114m	2.552ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	51.340m	16.828ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.049m	17.793ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.473m	6.206ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.473m	6.206ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.473m	6.206ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.540m	4.238ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.833m	5.304ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.254m	23.349ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.540m	4.238ms	1	1	100.00
		chip_sw_keymgr_key_derivation	14.230m	7.720ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.840m	4.644ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.202m	2.513ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.254m	23.349ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.540m	4.238ms	1	1	100.00
		chip_sw_keymgr_key_derivation	14.230m	7.720ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.840m	4.644ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.202m	2.513ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.833m	5.304ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.880m	4.322ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.960m	3.007ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.310m	3.475ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.327m	5.001ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.311m	6.103ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.705m	7.098ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.833m	5.304ms	1	1	100.00
		chip_prim_tl_access	4.301m	8.384ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.301m	8.384ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.307m	9.207ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.644m	7.218ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.193m	21.647ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.841m	6.908ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.259m	6.360ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.093m	5.583ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.222m	24.076ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.795m	14.618ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.974m	9.437ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.772m	12.716ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.301m	4.308ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.644m	7.218ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.690m	4.704ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	28.438m	38.671ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.012m	7.785ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.348m	4.445ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.380m	22.308ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.591m	6.423ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	17.076m	11.063ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.538m	28.437ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.449m	3.442ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.634m	5.938ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.171m	10.070ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.171m	10.070ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	17.076m	11.063ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.380m	22.308ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.301m	4.308ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.069m	4.892ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.117m	2.910ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.585m	4.438ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.294m	4.379ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.526m	11.823ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.768m	2.884ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.634m	5.938ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	18.582m	9.152ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.315m	4.639ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.665m	4.993ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.153m	2.899ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.202m	2.513ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.585m	4.438ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.585m	4.438ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	5.101m	6.496ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.319m	13.245ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.117m	2.910ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.650m	4.150ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.840m	7.297ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.885m	4.740ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.448m	11.952ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.513m	5.880ms	1	1	100.00
		chip_plic_all_irqs_10	4.398m	2.917ms	1	1	100.00
		chip_plic_all_irqs_20	6.091m	3.832ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.997m	2.805ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.135m	3.290ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.798m	14.535ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.783m	6.136ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.984m	3.005ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.215m	2.534ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.147m	3.331ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.840m	4.644ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.227m	4.444ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.037m	6.442ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.040m	8.841ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.020m	7.662ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.634m	5.938ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.013m	6.206ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.591m	6.423ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	14.067m	23.038ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.950m	2.643ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.923m	3.346ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.552m	4.327ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	14.067m	23.038ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	14.067m	23.038ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	35.862m	20.655ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	35.862m	20.655ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.075m	6.057ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.236m	35.249ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.729m	3.142ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.655m	2.465ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.919m	3.750ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.322m	3.493ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.973m	8.108ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.278h	31.398ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.744m	12.445ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.853m	3.155ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.252m	3.191ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.547m	2.749ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.351h	71.927ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.840m	3.442ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.120m	11.892ms	1	1	100.00
		rom_e2e_jtag_debug_dev	18.075m	11.897ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.917m	10.176ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.132m	3.678ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.929m	3.680ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.865m	3.844ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	18.974s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.960m	4.434ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.478m	2.621ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	9.036m	4.273ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	10.530m	6.138ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.378m	2.644ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.205m	5.833ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.018m	2.850ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.795m	4.497ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.198m	5.559ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.407m	5.738ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	17.076m	11.063ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.120m	11.892ms	1	1	100.00
		rom_e2e_jtag_debug_dev	18.075m	11.897ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.917m	10.176ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.034m	5.508ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.634m	5.938ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.401h	38.347ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.401h	38.347ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.581m	3.343ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	7.043m	5.143ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	46.460m	18.214ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.534m	2.476ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.610m	5.341ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.787m	2.657ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.961m	2.909ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.802m	4.162ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.317s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.320m	2.516ms	1	1	100.00
		TOTAL			286	325	88.00

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.58932688824647724343973260611815079757369516691292508439208996907679178729956
    Line 677, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.56195890600700100867360373427215247086043956058118893911762506353671555043532
    Line 667, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.95531661147808807469098185135917522358220445111068986413131706021456120724900
    Line 674, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.45441852395897451332227861964052148752421286682810539095539425565857841512476
    Line 628, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.29242166193473964101125846639795495889869741452800035488094906044931421993115
    Line 688, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.9904640235586856001267550458155048274623332443912906838435898710049372808055
    Line 593, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.37530417551137633806648156853268037150863949060800772960269819295373437974469
    Line 568, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.45462151844477418981566495915398178397278227970637165410861216664013168294644
    Line 589, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.57439025081116735460631406912700205741062678551422730444747507686122192620972
    Line 635, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.59582398790644996841552520808211857929028674029785384503581929489285455819787
    Line 665, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.107089869739336620049459804213363524054002249088835225891736266663793189388893
    Line 656, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.22897605170179450083619530530756634559410188894099508228135675744573065519671
    Line 773, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.19727544760127213489963101555504949074421710718672088174826124354316362241524
    Line 729, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.66551942330501326820754905305676874197932737941527702692310299746853304387900
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.354s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.74307143393636138480645313325913056242823803344975209722063386278904728427361
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 9.109s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.40337747552879797690699043850322048009715340458836001933630165760751822689876
    Line 725, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.18660903090661311752485176197644546317152393972435928649694626819142069275033
    Line 580, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.64846410225335376366323957457047603998493574245341127686022639830317160372189
    Line 696, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.10849145483372662170576779654640612204443926102584090364188482362174271161779
    Line 635, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.69881622139117021443996737007128303344283433084770756793603053366080916011228
    Line 647, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3460.533000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3460.533000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.15798129186676494088501020052491368570656848806350067050656887044392542826778
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3004.650088 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3004.650088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@84773) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.75745898612242996853816493495947686049540516268442191596278675840453183967558
Line 447, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4437.710376 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@84773) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4437.710376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.44323012835231074917404387952535701924285768531640686421860562584620466646016
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35248.683559 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35248.683559 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.88073634023325706475703833513040050939972272001845645883046652154479811749336
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2514.859112 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2514.859112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.43294793526222834172677405405476153330660841920808765375765593599057427353212
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3245.766398 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3245.766398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.2635841032828969403255628413986457100742951880933442280014838909886567776034
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2807.212824 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2807.212824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36713) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.44317355375209287954372322779304023812625477376194739973484968584870594799122
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2442.644868 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36713) { a_addr: 'h10718  a_data: 'h917e8488  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h1a998  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2442.644868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.70070661457586106371010953291270916845948267116173614700751000748729217504947
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3242.916000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3242.916000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.38178299275898390983890960111581402004378615291477964733599884252091521617311
    Line 441, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2683.427000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2683.427000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.97212991391889106947441017310644555217391691926248261808855475321112116222490
    Line 460, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 17786.444537 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 17786.444537 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.11578583020560629062644245133542458022820444647648628045460031623622943419233
    Line 494, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3441.692921 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3441.692921 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.114785332426156049382657046781466124052717544196542134017354688287372115298950
    Line 636, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2857356927588007473960697410294257142319547604173024153596677507428531055328
    Line 671, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```