ADC_CTRL Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	6.520s	6.045ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.850s	1.454ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.740s	553.825us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.136m	30.351ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.020s	1.319ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.100s	585.097us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.740s	553.825us	1	1	100.00
		adc_ctrl_csr_aliasing	5.020s	1.319ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.278m	493.124ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.441m	325.797ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.612m	165.390ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.113m	332.141ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	11.457m	397.821ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.770m	189.434ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.481m	434.427ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	13.631m	551.890ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.640s	4.380ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	58.360s	37.643ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.134m	110.694ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	44.580s	160.024ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.540s	489.003us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.110s	495.329us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.130s	665.897us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.130s	665.897us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.850s	1.454ms	1	1	100.00
		adc_ctrl_csr_rw	1.740s	553.825us	1	1	100.00
		adc_ctrl_csr_aliasing	5.020s	1.319ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.490s	2.219ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.850s	1.454ms	1	1	100.00
		adc_ctrl_csr_rw	1.740s	553.825us	1	1	100.00
		adc_ctrl_csr_aliasing	5.020s	1.319ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.490s	2.219ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	3.210s	4.544ms	1	1	100.00
		adc_ctrl_tl_intg_err	15.220s	7.943ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	15.220s	7.943ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.330s	15.718ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00