EDN Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.660s 53.017us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.640s 17.827us 1 1 100.00
V1 csr_rw edn_csr_rw 1.590s 67.247us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.100s 64.845us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.780s 38.650us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.220s 83.288us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.590s 67.247us 1 1 100.00
edn_csr_aliasing 1.780s 38.650us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.820s 40.421us 1 1 100.00
V2 csrng_commands edn_genbits 1.820s 40.421us 1 1 100.00
V2 genbits edn_genbits 1.820s 40.421us 1 1 100.00
V2 interrupts edn_intr 1.740s 26.230us 1 1 100.00
V2 alerts edn_alert 1.820s 20.618us 1 1 100.00
V2 errs edn_err 2.020s 41.318us 1 1 100.00
V2 disable edn_disable 1.630s 14.566us 1 1 100.00
edn_disable_auto_req_mode 1.910s 32.789us 1 1 100.00
V2 stress_all edn_stress_all 4.040s 856.637us 1 1 100.00
V2 intr_test edn_intr_test 1.620s 26.431us 1 1 100.00
V2 alert_test edn_alert_test 1.640s 36.653us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.600s 226.944us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.600s 226.944us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.640s 17.827us 1 1 100.00
edn_csr_rw 1.590s 67.247us 1 1 100.00
edn_csr_aliasing 1.780s 38.650us 1 1 100.00
edn_same_csr_outstanding 1.660s 17.773us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.640s 17.827us 1 1 100.00
edn_csr_rw 1.590s 67.247us 1 1 100.00
edn_csr_aliasing 1.780s 38.650us 1 1 100.00
edn_same_csr_outstanding 1.660s 17.773us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.640s 673.002us 1 1 100.00
edn_tl_intg_err 2.350s 57.679us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.700s 16.055us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.820s 20.618us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.640s 673.002us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.640s 673.002us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.640s 673.002us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.640s 673.002us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.820s 20.618us 1 1 100.00
edn_sec_cm 6.640s 673.002us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.820s 20.618us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.350s 57.679us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets