HMAC Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.470s 276.674us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.790s 38.946us 1 1 100.00
V1 csr_rw hmac_csr_rw 2.210s 36.124us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.830s 727.819us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.300s 402.116us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 8.451m 301.764ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 2.210s 36.124us 1 1 100.00
hmac_csr_aliasing 6.300s 402.116us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 10.520s 1.343ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.013m 1.451ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.096m 54.852ms 1 1 100.00
hmac_test_sha384_vectors 20.230s 977.308us 1 1 100.00
hmac_test_sha512_vectors 6.236m 11.209ms 1 1 100.00
hmac_test_hmac256_vectors 8.990s 291.856us 1 1 100.00
hmac_test_hmac384_vectors 10.370s 887.232us 1 1 100.00
hmac_test_hmac512_vectors 12.130s 917.153us 1 1 100.00
V2 burst_wr hmac_burst_wr 10.590s 4.665ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 14.443m 13.807ms 1 1 100.00
V2 error hmac_error 5.350s 74.727us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.135m 11.747ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.470s 276.674us 1 1 100.00
hmac_long_msg 10.520s 1.343ms 1 1 100.00
hmac_back_pressure 1.013m 1.451ms 1 1 100.00
hmac_datapath_stress 14.443m 13.807ms 1 1 100.00
hmac_burst_wr 10.590s 4.665ms 1 1 100.00
hmac_stress_all 3.075m 38.718ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.470s 276.674us 1 1 100.00
hmac_long_msg 10.520s 1.343ms 1 1 100.00
hmac_back_pressure 1.013m 1.451ms 1 1 100.00
hmac_datapath_stress 14.443m 13.807ms 1 1 100.00
hmac_wipe_secret 1.135m 11.747ms 1 1 100.00
hmac_test_sha256_vectors 3.096m 54.852ms 1 1 100.00
hmac_test_sha384_vectors 20.230s 977.308us 1 1 100.00
hmac_test_sha512_vectors 6.236m 11.209ms 1 1 100.00
hmac_test_hmac256_vectors 8.990s 291.856us 1 1 100.00
hmac_test_hmac384_vectors 10.370s 887.232us 1 1 100.00
hmac_test_hmac512_vectors 12.130s 917.153us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.470s 276.674us 1 1 100.00
hmac_long_msg 10.520s 1.343ms 1 1 100.00
hmac_back_pressure 1.013m 1.451ms 1 1 100.00
hmac_datapath_stress 14.443m 13.807ms 1 1 100.00
hmac_burst_wr 10.590s 4.665ms 1 1 100.00
hmac_error 5.350s 74.727us 1 1 100.00
hmac_wipe_secret 1.135m 11.747ms 1 1 100.00
hmac_test_sha256_vectors 3.096m 54.852ms 1 1 100.00
hmac_test_sha384_vectors 20.230s 977.308us 1 1 100.00
hmac_test_sha512_vectors 6.236m 11.209ms 1 1 100.00
hmac_test_hmac256_vectors 8.990s 291.856us 1 1 100.00
hmac_test_hmac384_vectors 10.370s 887.232us 1 1 100.00
hmac_test_hmac512_vectors 12.130s 917.153us 1 1 100.00
hmac_stress_all 3.075m 38.718ms 1 1 100.00
V2 stress_all hmac_stress_all 3.075m 38.718ms 1 1 100.00
V2 alert_test hmac_alert_test 1.840s 47.562us 1 1 100.00
V2 intr_test hmac_intr_test 1.500s 94.956us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.020s 867.961us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.020s 867.961us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.790s 38.946us 1 1 100.00
hmac_csr_rw 2.210s 36.124us 1 1 100.00
hmac_csr_aliasing 6.300s 402.116us 1 1 100.00
hmac_same_csr_outstanding 2.300s 192.789us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.790s 38.946us 1 1 100.00
hmac_csr_rw 2.210s 36.124us 1 1 100.00
hmac_csr_aliasing 6.300s 402.116us 1 1 100.00
hmac_same_csr_outstanding 2.300s 192.789us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.300s 123.217us 1 1 100.00
hmac_tl_intg_err 3.440s 350.567us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.440s 350.567us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.470s 276.674us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.500s 585.913us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.797m 27.129ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.030s 15.622us 1 1 100.00
TOTAL 28 28 100.00