I2C Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: `601f9c3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	18.260s	4.506ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	23.230s	1.846ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.710s	24.905us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.680s	20.659us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.400s	368.298us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.320s	467.488us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.760s	149.855us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.680s	20.659us	1	1	100.00
		i2c_csr_aliasing	2.320s	467.488us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.710s	299.327us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	5.664m	61.698ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.471m	5.333ms	1	1	100.00
V2	host_override	i2c_host_override	1.560s	86.754us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.399m	9.076ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.433m	7.999ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.990s	266.989us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.920s	1.573ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.730s	244.030us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	50.820s	19.298ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.860s	1.033ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.760s	802.694us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.680s	1.982ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	49.480s	14.981ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.740s	488.327us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	26.870s	835.903us	1	1	100.00
		i2c_target_intr_smoke	4.500s	5.633ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.770s	182.085us	1	1	100.00
		i2c_target_fifo_reset_tx	1.980s	461.543us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	6.778m	47.278ms	1	1	100.00
		i2c_target_stress_rd	26.870s	835.903us	1	1	100.00
		i2c_target_intr_stress_wr	3.844m	20.207ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.980s	3.095ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	5.870s	2.151ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.940s	1.138ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.300s	1.957ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.100s	1.406ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.170s	561.083us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.471m	5.333ms	1	1	100.00
		i2c_host_perf_precise	10.690s	2.939ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.860s	1.033ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.140s	451.669us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.930s	2.299ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.900s	488.688us	1	1	100.00
		i2c_target_nack_txstretch	2.370s	740.717us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.700s	244.238us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.970s	472.071us	1	1	100.00
V2	alert_test	i2c_alert_test	1.630s	16.960us	1	1	100.00
V2	intr_test	i2c_intr_test	1.720s	46.818us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.300s	51.068us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.300s	51.068us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.710s	24.905us	1	1	100.00
		i2c_csr_rw	1.680s	20.659us	1	1	100.00
		i2c_csr_aliasing	2.320s	467.488us	1	1	100.00
		i2c_same_csr_outstanding	2.120s	32.149us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.710s	24.905us	1	1	100.00
		i2c_csr_rw	1.680s	20.659us	1	1	100.00
		i2c_csr_aliasing	2.320s	467.488us	1	1	100.00
		i2c_same_csr_outstanding	2.120s	32.149us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.670s	579.319us	1	1	100.00
		i2c_sec_cm	1.750s	525.509us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.670s	579.319us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	6.690s	542.060us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.600s	270.162us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.640s	631.934us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.90390846145944076718570468684884211878544162504385816978795234911264245920226
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 542059613 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 542059613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.15836624021088741806334733347451823387110927050542217037939113507513469034724
    Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 631933803 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 631933803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.5403184580552029286025820842248823646185160432328964559404018045410887417876
Line 195, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 61697708994 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @8857996

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.84229559034000656202618613997060225438262933351227262047887072324259372403132
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 270161662 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 270161662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
- Test i2c_target_nack_txstretch has 1 failures.
  - 0.i2c_target_nack_txstretch.316386658780815261186440690336228581223421845263031350199543987947538572768
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 740716558 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 740716558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```