KEYMGR Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.780s	113.747us	1	1	100.00
V1	random	keymgr_random	4.090s	202.877us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.700s	47.183us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.550s	16.113us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.570s	865.765us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.780s	734.034us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.650s	17.274us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.550s	16.113us	1	1	100.00
		keymgr_csr_aliasing	9.780s	734.034us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	3.270s	89.865us	1	1	100.00
V2	sideload	keymgr_sideload	2.640s	160.502us	1	1	100.00
		keymgr_sideload_kmac	17.290s	1.412ms	1	1	100.00
		keymgr_sideload_aes	4.510s	486.053us	1	1	100.00
		keymgr_sideload_otbn	3.020s	56.268us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.060s	101.819us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.700s	49.657us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.870s	101.465us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.140s	126.666us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.860s	81.237us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.200s	253.026us	1	1	100.00
V2	stress_all	keymgr_stress_all	14.640s	519.790us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.480s	27.420us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.680s	41.585us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.240s	58.154us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.240s	58.154us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.700s	47.183us	1	1	100.00
		keymgr_csr_rw	1.550s	16.113us	1	1	100.00
		keymgr_csr_aliasing	9.780s	734.034us	1	1	100.00
		keymgr_same_csr_outstanding	2.220s	42.517us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.700s	47.183us	1	1	100.00
		keymgr_csr_rw	1.550s	16.113us	1	1	100.00
		keymgr_csr_aliasing	9.780s	734.034us	1	1	100.00
		keymgr_same_csr_outstanding	2.220s	42.517us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
		keymgr_tl_intg_err	4.540s	310.681us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.200s	487.032us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.200s	487.032us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.200s	487.032us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.200s	487.032us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.540s	235.935us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.540s	310.681us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.200s	487.032us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.270s	89.865us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.090s	202.877us	1	1	100.00
		keymgr_csr_rw	1.550s	16.113us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.090s	202.877us	1	1	100.00
		keymgr_csr_rw	1.550s	16.113us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.090s	202.877us	1	1	100.00
		keymgr_csr_rw	1.550s	16.113us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.700s	49.657us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.860s	81.237us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.860s	81.237us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.090s	202.877us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	10.650s	705.658us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.740s	62.381us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.700s	49.657us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.740s	62.381us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.740s	62.381us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.740s	62.381us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.980s	656.611us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.740s	62.381us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	10.850s	4.184ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.11666279448868273418099347900968081111496846258016597090467799670279516168265
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
        UVM_ERROR @  17273598 ps: (keymgr_csr_assert_fpv.sv:399) [ASSERT FAILED] sealing_sw_binding_1_rd_A
        UVM_INFO @  17273598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---