KMAC/MASKED Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	11.350s	730.576us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.650s	24.878us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.740s	48.170us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.680s	1.410ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.690s	2.053ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.730s	34.494us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.740s	48.170us	1	1	100.00
		kmac_csr_aliasing	7.690s	2.053ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.650s	17.945us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.830s	32.271us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	15.925m	171.322ms	1	1	100.00
V2	burst_write	kmac_burst_write	11.607m	9.123ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.480s	2.297ms	1	1	100.00
		kmac_test_vectors_sha3_256	32.165m	325.574ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.299m	43.957ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.123m	9.566ms	1	1	100.00
		kmac_test_vectors_shake_128	37.459m	139.981ms	1	1	100.00
		kmac_test_vectors_shake_256	4.845m	20.511ms	1	1	100.00
		kmac_test_vectors_kmac	2.600s	151.085us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.140s	1.002ms	1	1	100.00
V2	sideload	kmac_sideload	2.788m	45.996ms	1	1	100.00
V2	app	kmac_app	3.607m	44.520ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	34.200s	5.097ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.215m	6.575ms	1	1	100.00
V2	error	kmac_error	5.144m	70.760ms	1	1	100.00
V2	key_error	kmac_key_error	3.520s	200.067us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.680s	136.481us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.880s	63.718us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.710s	48.294us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	13.150s	3.640ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.270s	74.525us	1	1	100.00
V2	stress_all	kmac_stress_all	9.014m	39.617ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.770s	15.580us	1	1	100.00
V2	alert_test	kmac_alert_test	1.730s	59.285us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.130s	251.566us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.130s	251.566us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.650s	24.878us	1	1	100.00
		kmac_csr_rw	1.740s	48.170us	1	1	100.00
		kmac_csr_aliasing	7.690s	2.053ms	1	1	100.00
		kmac_same_csr_outstanding	2.130s	219.890us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.650s	24.878us	1	1	100.00
		kmac_csr_rw	1.740s	48.170us	1	1	100.00
		kmac_csr_aliasing	7.690s	2.053ms	1	1	100.00
		kmac_same_csr_outstanding	2.130s	219.890us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.880s	41.733us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.880s	41.733us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.880s	41.733us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.880s	41.733us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.110s	111.915us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.186m	90.904ms	1	1	100.00
		kmac_tl_intg_err	2.740s	57.386us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.740s	57.386us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.270s	74.525us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	11.350s	730.576us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.788m	45.996ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.880s	41.733us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.186m	90.904ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.186m	90.904ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.186m	90.904ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	11.350s	730.576us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.270s	74.525us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.186m	90.904ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.219m	30.430ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	11.350s	730.576us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.870s	23.278ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.86428067001033589304016393126549110129600572669837766523146986496866455124362
      Line 163, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23278352741 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 23278352741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---