KMAC/UNMASKED Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	5.440s	435.222us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.760s	102.195us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.620s	36.166us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.100s	4.191ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.280s	141.039us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.230s	24.912us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.620s	36.166us	1	1	100.00
		kmac_csr_aliasing	6.280s	141.039us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.710s	11.042us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.200s	38.298us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	26.816m	61.626ms	1	1	100.00
V2	burst_write	kmac_burst_write	11.012m	33.704ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.970s	11.252ms	1	1	100.00
		kmac_test_vectors_sha3_256	34.850s	2.470ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.500s	1.663ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.110s	2.088ms	1	1	100.00
		kmac_test_vectors_shake_128	31.273m	1.013s	1	1	100.00
		kmac_test_vectors_shake_256	16.568m	16.560ms	1	1	100.00
		kmac_test_vectors_kmac	2.810s	124.379us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.770s	122.290us	1	1	100.00
V2	sideload	kmac_sideload	3.849m	4.196ms	1	1	100.00
V2	app	kmac_app	1.575m	3.350ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.381m	22.041ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.723m	14.826ms	1	1	100.00
V2	error	kmac_error	51.740s	1.037ms	1	1	100.00
V2	key_error	kmac_key_error	3.700s	2.335ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	21.420s	10.037ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	23.830s	434.327us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	3.500s	217.672us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	9.200s	1.778ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.070s	62.281us	1	1	100.00
V2	stress_all	kmac_stress_all	5.794m	39.472ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.560s	27.309us	1	1	100.00
V2	alert_test	kmac_alert_test	1.660s	76.102us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.530s	147.507us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.530s	147.507us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.760s	102.195us	1	1	100.00
		kmac_csr_rw	1.620s	36.166us	1	1	100.00
		kmac_csr_aliasing	6.280s	141.039us	1	1	100.00
		kmac_same_csr_outstanding	2.700s	372.665us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.760s	102.195us	1	1	100.00
		kmac_csr_rw	1.620s	36.166us	1	1	100.00
		kmac_csr_aliasing	6.280s	141.039us	1	1	100.00
		kmac_same_csr_outstanding	2.700s	372.665us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.100s	110.737us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.100s	110.737us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.100s	110.737us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.100s	110.737us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.230s	616.904us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	17.730s	6.873ms	1	1	100.00
		kmac_tl_intg_err	2.540s	202.574us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.540s	202.574us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.070s	62.281us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	5.440s	435.222us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.849m	4.196ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.100s	110.737us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	17.730s	6.873ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	17.730s	6.873ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	17.730s	6.873ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	5.440s	435.222us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.070s	62.281us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	17.730s	6.873ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.500s	94.839us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	5.440s	435.222us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.916m	8.290ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.108529879814850167380139952828947217655185582741070119179177941987162357370908
      Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10036516472 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x75f5000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10036516472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.11714214821946459337195411527221581686053317424366238793720096484952052387321
      Line 169, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8290184978 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 8290184978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.92973080218714458687045911464621378686135556565805285541169730465546116271566
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
        UVM_ERROR @ 616903732 ps: (kmac_csr_assert_fpv.sv:540) [ASSERT FAILED] prefix_9_rd_A
        UVM_INFO @ 616903732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---