OTBN Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	38.797us	1	1	100.00
V1	single_binary	otbn_single	9.000s	58.689us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	59.196us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	19.014us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	82.746us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	161.996us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	604.853us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	19.014us	1	1	100.00
		otbn_csr_aliasing	6.000s	161.996us	1	1	100.00
V1	mem_walk	otbn_mem_walk	15.000s	744.602us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	17.000s	2.676ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	26.000s	346.960us	1	1	100.00
V2	multi_error	otbn_multi_err	47.000s	953.595us	1	1	100.00
V2	back_to_back	otbn_multi	34.000s	172.876us	1	1	100.00
V2	stress_all	otbn_stress_all	48.000s	389.484us	1	1	100.00
V2	lc_escalation	otbn_escalate	10.000s	54.164us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	28.566us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	12.000s	85.069us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	20.477us	1	1	100.00
V2	intr_test	otbn_intr_test	14.000s	18.186us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	46.000s	75.023us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	46.000s	75.023us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	59.196us	1	1	100.00
		otbn_csr_rw	7.000s	19.014us	1	1	100.00
		otbn_csr_aliasing	6.000s	161.996us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	30.978us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	59.196us	1	1	100.00
		otbn_csr_rw	7.000s	19.014us	1	1	100.00
		otbn_csr_aliasing	6.000s	161.996us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	30.978us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	11.000s	38.038us	1	1	100.00
		otbn_dmem_err	16.000s	46.273us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	17.397us	1	1	100.00
		otbn_controller_ispr_rdata_err	11.000s	206.049us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	213.411us	1	1	100.00
		otbn_urnd_err	7.000s	10.117us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	23.153us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	24.151us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	74.671us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
		otbn_tl_intg_err	56.000s	119.720us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.000m	116.441us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	38.797us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	46.273us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	38.038us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	56.000s	119.720us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	10.000s	54.164us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	38.038us	1	1	100.00
		otbn_dmem_err	16.000s	46.273us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	28.566us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	23.153us	1	1	100.00
		otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	58.689us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	38.038us	1	1	100.00
		otbn_dmem_err	16.000s	46.273us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	28.566us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	23.153us	1	1	100.00
		otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	10.000s	54.164us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	38.038us	1	1	100.00
		otbn_dmem_err	16.000s	46.273us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	28.566us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	23.153us	1	1	100.00
		otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	58.689us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	7.000s	34.053us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	48.238us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	33.000s	1.917ms	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	33.000s	1.917ms	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	56.859us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	101.111us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	46.770us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	46.770us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	9.804us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	58.689us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	58.689us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	58.689us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	34.000s	172.876us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	58.689us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	58.689us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	32.351us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	58.689us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.000m	2.153ms	1	1	100.00
V2S		TOTAL			20	20	100.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.367m	5.226ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			40	41	97.56

Failure Buckets

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.21980577732707158841594858873404670311626673466043101611718672049627855749746
      Line 559, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 5225676808 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 5225676808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---