PATTGEN Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	16.000s	41.418us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	24.745us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	17.245us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	135.894us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	21.589us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	29.284us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	17.245us	1	1	100.00
		pattgen_csr_aliasing	4.000s	21.589us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	9.733m	23.628ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	4.000s	44.314us	1	1	100.00
V2	error	pattgen_error	13.000s	18.358us	1	1	100.00
V2	stress_all	pattgen_stress_all	5.000s	781.551us	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	24.406us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	72.644us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	63.646us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	63.646us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	24.745us	1	1	100.00
		pattgen_csr_rw	4.000s	17.245us	1	1	100.00
		pattgen_csr_aliasing	4.000s	21.589us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	127.012us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	24.745us	1	1	100.00
		pattgen_csr_rw	4.000s	17.245us	1	1	100.00
		pattgen_csr_aliasing	4.000s	21.589us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	127.012us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	152.361us	1	1	100.00
		pattgen_sec_cm	4.000s	62.678us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	152.361us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	1.350m	4.646ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	476.411us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.89928577949680744119969083049833339435110841159663208869640103035477711563326
      Line 266, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2500651424 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 2500660684 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2500660684 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 4/10
        UVM_INFO @ 2500715629 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.25799549172630607854231038651695861328137494097339083058936547702581318385231
      Line 134, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @ 781551467 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        ------------------------------------
        Name      Type          Size  Value
        ------------------------------------
        exp_item  pattgen_item  -     @11035