ROM_CTRL/64KB Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.730s 558.185us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.420s 224.580us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.750s 1.075ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.850s 673.812us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 8.280s 290.158us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.050s 815.967us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.750s 1.075ms 1 1 100.00
rom_ctrl_csr_aliasing 8.280s 290.158us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.780s 533.130us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 8.480s 297.793us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.660s 312.637us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 26.420s 838.097us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.500s 1.372ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.050s 743.556us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.840s 727.494us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.840s 727.494us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.420s 224.580us 1 1 100.00
rom_ctrl_csr_rw 6.750s 1.075ms 1 1 100.00
rom_ctrl_csr_aliasing 8.280s 290.158us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.090s 790.571us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.420s 224.580us 1 1 100.00
rom_ctrl_csr_rw 6.750s 1.075ms 1 1 100.00
rom_ctrl_csr_aliasing 8.280s 290.158us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.090s 790.571us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.057m 49.837ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 26.580s 12.620ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.035m 1.103ms 1 1 100.00
rom_ctrl_tl_intg_err 34.790s 2.290ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.035m 1.103ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.035m 1.103ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.057m 49.837ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.057m 49.837ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.057m 49.837ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.057m 49.837ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.057m 49.837ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.035m 1.103ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.035m 1.103ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.730s 558.185us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.730s 558.185us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.730s 558.185us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 34.790s 2.290ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.057m 49.837ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.500s 1.372ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.057m 49.837ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.057m 49.837ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.057m 49.837ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 26.580s 12.620ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.035m 1.103ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 45.430s 4.193ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00