RV_DM/USE_JTAG_INTERFACE Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.050s 721.257us 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.650s 135.923us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.110s 583.789us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 41.780s 18.978ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.100s 881.720us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 6.770s 3.390ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 5.520s 4.051ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 16.180s 8.544ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.822m 119.891ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.570s 523.135us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.860s 146.697us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.620s 500.697us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.440s 600.670us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.000s 88.157us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.140s 1.136ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.890s 252.887us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.900s 426.974us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.570s 523.135us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.690s 408.303us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 3.010s 535.085us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.620s 500.697us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.740s 214.891us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.960s 286.612us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.380s 63.338us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 27.380s 10.278ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 44.850s 4.387ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.720s 39.285us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 44.850s 4.387ms 1 1 100.00
rv_dm_csr_rw 2.380s 63.338us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.570s 55.655us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.630s 33.140us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 2.050s 721.257us 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.620s 213.778us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.860s 86.805us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.580s 321.988us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.590s 2.232ms 1 1 100.00
V2 sba rv_dm_sba_tl_access 2.920s 2.411ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 2.030s 194.043us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 3.480s 3.182ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 29.420s 86.729ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.870s 630.878us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.630s 1.211ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.240s 288.574us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 2.130s 334.855us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 5.120s 10.606ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.800s 27.655us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.750s 395.199us 1 1 100.00
V2 stress_all rv_dm_stress_all 7.180s 2.530ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.720s 39.671us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 2.220s 121.436us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 2.220s 121.436us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 44.850s 4.387ms 1 1 100.00
rv_dm_csr_hw_reset 2.960s 286.612us 1 1 100.00
rv_dm_csr_rw 2.380s 63.338us 1 1 100.00
rv_dm_same_csr_outstanding 8.020s 520.861us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 44.850s 4.387ms 1 1 100.00
rv_dm_csr_hw_reset 2.960s 286.612us 1 1 100.00
rv_dm_csr_rw 2.380s 63.338us 1 1 100.00
rv_dm_same_csr_outstanding 8.020s 520.861us 1 1 100.00
V2 TOTAL 16 19 84.21
V2S tl_intg_err rv_dm_sec_cm 2.810s 430.033us 1 1 100.00
rv_dm_tl_intg_err 8.740s 2.147ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 8.740s 2.147ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.630s 1.211ms 1 1 100.00
rv_dm_debug_disabled 1.710s 51.816us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.630s 1.211ms 1 1 100.00
rv_dm_debug_disabled 1.710s 51.816us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 2.050s 721.257us 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.560s 500.132us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.060s 158.301us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.060s 158.301us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.560s 500.132us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.730s 27.798us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.630s 24.874us 1 1 100.00
TOTAL 48 53 90.57

Failure Buckets