RV_TIMER Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.490s	37.437us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.470s	17.315us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.420s	13.315us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.400s	194.564us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.880s	41.911us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.640s	123.922us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.420s	13.315us	1	1	100.00
		rv_timer_csr_aliasing	1.880s	41.911us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.550s	102.397us	1	1	100.00
V2	disabled	rv_timer_disabled	1.810s	815.089us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	4.625m	739.814ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	4.625m	739.814ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.950s	907.546us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.350s	35.987us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.460s	90.057us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.840s	53.676us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.840s	53.676us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.470s	17.315us	1	1	100.00
		rv_timer_csr_rw	1.420s	13.315us	1	1	100.00
		rv_timer_csr_aliasing	1.880s	41.911us	1	1	100.00
		rv_timer_same_csr_outstanding	1.690s	41.085us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.470s	17.315us	1	1	100.00
		rv_timer_csr_rw	1.420s	13.315us	1	1	100.00
		rv_timer_csr_aliasing	1.880s	41.911us	1	1	100.00
		rv_timer_same_csr_outstanding	1.690s	41.085us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.110s	868.499us	1	1	100.00
		rv_timer_tl_intg_err	2.200s	152.138us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.200s	152.138us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	37.240s	13.736ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.490s	30.071us	1	1	100.00
		rv_timer_max	1.840s	14.161us	1	1	100.00
		TOTAL			19	19	100.00