SPI_DEVICE/1R1W Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.030s	11.767ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.860s	110.860us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.330s	88.579us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.490s	527.670us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.090s	453.326us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.500s	53.309us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.330s	88.579us	1	1	100.00
		spi_device_csr_aliasing	6.090s	453.326us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.710s	37.146us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.400s	83.733us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.750s	20.655us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.570s	2.259us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.670s	5.206us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.980s	330.984us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.980s	330.984us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.660s	1.321ms	1	1	100.00
		spi_device_tpm_sts_read	1.770s	265.786us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	16.130s	3.979ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.510s	1.763ms	1	1	100.00
		spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.100s	622.861us	1	1	100.00
		spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.100s	622.861us	1	1	100.00
		spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.880s	90.997us	1	1	100.00
		spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.880s	90.997us	1	1	100.00
		spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.880s	90.997us	1	1	100.00
		spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.880s	90.997us	1	1	100.00
		spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.880s	90.997us	1	1	100.00
		spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	8.410s	2.229ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	13.960s	20.713ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	13.960s	20.713ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	13.960s	20.713ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.350s	706.797us	1	1	100.00
		spi_device_read_buffer_direct	4.810s	167.534us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	13.960s	20.713ms	1	1	100.00
		spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	52.280s	52.659ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.000s	196.000us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.000s	196.000us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.030s	11.767ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.282m	56.788ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.124m	24.506ms	1	1	100.00
V2	alert_test	spi_device_alert_test	2.070s	40.769us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.690s	47.442us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.480s	146.904us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.480s	146.904us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.860s	110.860us	1	1	100.00
		spi_device_csr_rw	2.330s	88.579us	1	1	100.00
		spi_device_csr_aliasing	6.090s	453.326us	1	1	100.00
		spi_device_same_csr_outstanding	3.380s	428.455us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.860s	110.860us	1	1	100.00
		spi_device_csr_rw	2.330s	88.579us	1	1	100.00
		spi_device_csr_aliasing	6.090s	453.326us	1	1	100.00
		spi_device_same_csr_outstanding	3.380s	428.455us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.880s	115.693us	1	1	100.00
		spi_device_tl_intg_err	6.170s	680.736us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.170s	680.736us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.071m	8.517ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.51611394090294578542532105167818235206810311897449505305932075463222326120026
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1799355 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[89])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1799355 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1799355 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[985])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.92690665010241961800090335360432351154369149527629241073460483319773088265528
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2953699 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf7a36a [111101111010001101101010] vs 0x0 [0])
        UVM_ERROR @   2960699 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7a2624 [11110100010011000100100] vs 0x0 [0])
        UVM_ERROR @   2999699 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x69267d [11010010010011001111101] vs 0x0 [0])
        UVM_ERROR @   3032699 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x168285 [101101000001010000101] vs 0x0 [0])
        UVM_ERROR @   3037699 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x75a889 [11101011010100010001001] vs 0x0 [0])