SPI_DEVICE/2P Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.140s	1.810ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.430s	45.043us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.810s	378.565us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.570s	1.291ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.720s	3.651ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.730s	97.205us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.810s	378.565us	1	1	100.00
		spi_device_csr_aliasing	17.720s	3.651ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.630s	13.976us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.010s	269.639us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.610s	27.941us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.800s	120.678us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	2.060s	15.929us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.320s	140.881us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.320s	140.881us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.280s	1.661ms	1	1	100.00
		spi_device_tpm_sts_read	1.790s	88.398us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	8.990s	2.152ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.900s	2.906ms	1	1	100.00
		spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	8.980s	12.789ms	1	1	100.00
		spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	8.980s	12.789ms	1	1	100.00
		spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	17.490s	5.600ms	1	1	100.00
		spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	17.490s	5.600ms	1	1	100.00
		spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	17.490s	5.600ms	1	1	100.00
		spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	17.490s	5.600ms	1	1	100.00
		spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	17.490s	5.600ms	1	1	100.00
		spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	13.100s	11.006ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	8.300s	3.130ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	8.300s	3.130ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	8.300s	3.130ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.400s	835.460us	1	1	100.00
		spi_device_read_buffer_direct	6.770s	373.330us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	8.300s	3.130ms	1	1	100.00
		spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	47.060s	28.032ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.710s	640.602us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.710s	640.602us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.140s	1.810ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.900s	6.773ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.320m	27.409ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.620s	29.428us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.630s	29.537us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.260s	346.942us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.260s	346.942us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.430s	45.043us	1	1	100.00
		spi_device_csr_rw	2.810s	378.565us	1	1	100.00
		spi_device_csr_aliasing	17.720s	3.651ms	1	1	100.00
		spi_device_same_csr_outstanding	3.640s	61.474us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.430s	45.043us	1	1	100.00
		spi_device_csr_rw	2.810s	378.565us	1	1	100.00
		spi_device_csr_aliasing	17.720s	3.651ms	1	1	100.00
		spi_device_same_csr_outstanding	3.640s	61.474us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.330s	76.641us	1	1	100.00
		spi_device_tl_intg_err	11.190s	1.141ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.190s	1.141ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.701m	15.939ms	1	1	100.00
		TOTAL			33	33	100.00