SRAM_CTRL/RET Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.140s	254.416us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.490s	23.621us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.060s	45.596us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.520s	164.422us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.850s	111.863us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.560s	144.844us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.060s	45.596us	1	1	100.00
		sram_ctrl_csr_aliasing	1.850s	111.863us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.470s	74.192us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.510s	679.754us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.170m	1.361ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.556m	45.832ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	37.320s	6.412ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.850m	6.842ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.680s	698.625us	1	1	100.00
V2	executable	sram_ctrl_executable	9.698m	11.881ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	54.610s	2.649ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.144m	12.222ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	47.010s	1.581ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	28.290s	280.682us	1	1	100.00
		sram_ctrl_throughput_w_readback	9.190s	212.559us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.396m	7.873ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.570s	30.649us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	5.873m	13.348ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.910s	179.630us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.470s	1.364ms	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.470s	1.364ms	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.490s	23.621us	1	1	100.00
		sram_ctrl_csr_rw	2.060s	45.596us	1	1	100.00
		sram_ctrl_csr_aliasing	1.850s	111.863us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	51.937us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.490s	23.621us	1	1	100.00
		sram_ctrl_csr_rw	2.060s	45.596us	1	1	100.00
		sram_ctrl_csr_aliasing	1.850s	111.863us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	51.937us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.840s	249.017us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.540s	3.732us	0	1	0.00
		sram_ctrl_tl_intg_err	2.700s	311.823us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.540s	3.732us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.700s	311.823us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.396m	7.873ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.396m	7.873ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.060s	45.596us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.698m	11.881ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.698m	11.881ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.698m	11.881ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.680s	698.625us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.010s	130.443us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.840s	249.017us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.120s	71.664us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.140s	254.416us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.140s	254.416us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.698m	11.881ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.540s	3.732us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.680s	698.625us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.540s	3.732us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.540s	3.732us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.140s	254.416us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.540s	3.732us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.129m	4.342ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.32956174554963769368105440638548540033981605525260475643988589178646860659310
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3732162 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3732162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---