SYSRST_CTRL Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.880s 2.168ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 6.930s 2.443ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 3.880s 2.189ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 3.310s 2.549ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 2.570s 4.091ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 3.980s 2.035ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 2.675m 39.630ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 9.650s 2.891ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 7.250s 2.082ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 3.980s 2.035ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.650s 2.891ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 47.080s 99.915ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 2.049m 65.686ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 3.110s 3.507ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 8.860s 3.542ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 3.930s 2.513ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.310s 2.180ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 2.090s 3.227ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 1.830s 2.843ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.440s 7.874ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.165m 33.413ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 3.650s 14.131ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.320s 2.030ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.180s 2.112ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.930s 3.335ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.930s 3.335ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 2.570s 4.091ms 1 1 100.00
sysrst_ctrl_csr_rw 3.980s 2.035ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.650s 2.891ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.330s 7.448ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 2.570s 4.091ms 1 1 100.00
sysrst_ctrl_csr_rw 3.980s 2.035ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.650s 2.891ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.330s 7.448ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 40.520s 22.008ms 1 1 100.00
sysrst_ctrl_tl_intg_err 44.040s 42.453ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 44.040s 42.453ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 12.650s 4.878ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00