UART Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.970s	123.448us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.410s	15.644us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.400s	19.221us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.480s	868.531us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.780s	31.641us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.550s	70.910us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.400s	19.221us	1	1	100.00
		uart_csr_aliasing	1.780s	31.641us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.828m	86.304ms	1	1	100.00
V2	parity	uart_smoke	1.970s	123.448us	1	1	100.00
		uart_tx_rx	1.828m	86.304ms	1	1	100.00
V2	parity_error	uart_intr	35.240s	13.282ms	1	1	100.00
		uart_rx_parity_err	22.530s	75.827ms	1	1	100.00
V2	watermark	uart_tx_rx	1.828m	86.304ms	1	1	100.00
		uart_intr	35.240s	13.282ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.598m	79.144ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.495m	96.788ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	4.931m	101.807ms	1	1	100.00
V2	rx_frame_err	uart_intr	35.240s	13.282ms	1	1	100.00
V2	rx_break_err	uart_intr	35.240s	13.282ms	1	1	100.00
V2	rx_timeout	uart_intr	35.240s	13.282ms	1	1	100.00
V2	perf	uart_perf	4.311m	17.244ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.090s	767.400us	1	1	100.00
V2	line_loopback	uart_loopback	2.090s	767.400us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	2.199m	83.768ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.240s	5.633ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.790s	1.270ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	48.030s	7.334ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.350m	94.302ms	1	1	100.00
V2	stress_all	uart_stress_all	1.432m	275.826ms	1	1	100.00
V2	alert_test	uart_alert_test	1.960s	15.383us	1	1	100.00
V2	intr_test	uart_intr_test	1.550s	43.760us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.240s	62.272us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.240s	62.272us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.410s	15.644us	1	1	100.00
		uart_csr_rw	1.400s	19.221us	1	1	100.00
		uart_csr_aliasing	1.780s	31.641us	1	1	100.00
		uart_same_csr_outstanding	1.680s	48.534us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.410s	15.644us	1	1	100.00
		uart_csr_rw	1.400s	19.221us	1	1	100.00
		uart_csr_aliasing	1.780s	31.641us	1	1	100.00
		uart_same_csr_outstanding	1.680s	48.534us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.670s	63.442us	1	1	100.00
		uart_tl_intg_err	1.990s	114.583us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.990s	114.583us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	35.610s	6.182ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00