CHIP Simulation Results

Thursday May 22 2025 20:17:00 UTC

GitHub Revision: `601f9c3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.983m	2.919ms	1	1	100.00
		chip_sw_example_rom	1.330m	2.889ms	1	1	100.00
		chip_sw_example_manufacturer	2.024m	2.481ms	1	1	100.00
		chip_sw_example_concurrency	2.097m	2.810ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.322m	6.280ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.182m	6.584ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	3.236m	4.491ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	45.478m	25.311ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	55.060s	2.308ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	45.478m	25.311ms	1	1	100.00
		chip_csr_rw	5.182m	6.584ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.470s	42.921us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.604m	4.418ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.604m	4.418ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.604m	4.418ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.624m	4.544ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.624m	4.544ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.684m	4.752ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.509m	4.516ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.003m	3.676ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.291m	3.340ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	15.542m	8.062ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.631m	3.383ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.273m	4.159ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.273m	4.159ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.256m	3.206ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.583m	2.759ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.282m	3.369ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	10.094m	9.555ms	1	1	100.00
		chip_tap_straps_testunlock0	3.846m	5.034ms	1	1	100.00
		chip_tap_straps_rma	10.985m	10.396ms	1	1	100.00
		chip_tap_straps_prod	1.597m	2.922ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	16.611s		0	1	0.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	16.654s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.646m	4.977ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.646m	4.977ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.935m	7.595ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	41.525m	24.632ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.218m	3.987ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.459m	6.311ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.922m	17.465ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.994m	3.201ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.954m	7.040ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.415m	3.155ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.673m	13.189ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.576m	2.854ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.450m	4.117ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.885m	2.055ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.342m	3.058ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.596m	8.455ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.553m	5.098ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.654m	3.253ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.553m	5.098ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.696m	2.530ms	1	1	100.00
		chip_sw_aes_smoketest	2.284m	2.538ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.893m	2.586ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.514m	3.127ms	1	1	100.00
		chip_sw_csrng_smoketest	2.148m	2.196ms	1	1	100.00
		chip_sw_entropy_src_smoketest	5.907m	4.454ms	1	1	100.00
		chip_sw_gpio_smoketest	3.057m	3.686ms	1	1	100.00
		chip_sw_hmac_smoketest	3.258m	3.773ms	1	1	100.00
		chip_sw_kmac_smoketest	3.025m	3.399ms	1	1	100.00
		chip_sw_otbn_smoketest	8.116m	5.636ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.401m	6.211ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.372m	5.466ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.618m	3.343ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.680m	2.590ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.484m	2.906ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.811m	2.491ms	1	1	100.00
		chip_sw_uart_smoketest	2.843m	3.079ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.904m	2.871ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.814m	5.301ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.982h	60.122ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.260m	15.065ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.311m	4.255ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.916m	3.379ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.467m	2.700ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.872h	53.025ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.859h	57.354ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	58.770s	2.088ms	1	1	100.00
V2	tl_d_illegal_access	chip_tl_errors	58.770s	2.088ms	1	1	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	45.478m	25.311ms	1	1	100.00
		chip_same_csr_outstanding	41.754m	28.365ms	1	1	100.00
		chip_csr_hw_reset	3.322m	6.280ms	1	1	100.00
		chip_csr_rw	5.182m	6.584ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	45.478m	25.311ms	1	1	100.00
		chip_same_csr_outstanding	41.754m	28.365ms	1	1	100.00
		chip_csr_hw_reset	3.322m	6.280ms	1	1	100.00
		chip_csr_rw	5.182m	6.584ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	31.250s	576.995us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.580s	43.967us	1	1	100.00
		xbar_smoke_large_delays	53.520s	9.502ms	1	1	100.00
		xbar_smoke_slow_rsp	51.040s	5.862ms	1	1	100.00
		xbar_random_zero_delays	10.700s	163.262us	1	1	100.00
		xbar_random_large_delays	1.538m	15.848ms	1	1	100.00
		xbar_random_slow_rsp	2.791m	21.355ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	5.620s	45.561us	1	1	100.00
		xbar_error_and_unmapped_addr	11.340s	171.606us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	21.880s	492.039us	1	1	100.00
		xbar_error_and_unmapped_addr	11.340s	171.606us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.042m	3.281ms	1	1	100.00
		xbar_access_same_device_slow_rsp	2.697m	20.325ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	24.020s	1.149ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	55.910s	1.465ms	1	1	100.00
		xbar_stress_all_with_error	3.518m	5.566ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.370s	7.620us	1	1	100.00
		xbar_stress_all_with_reset_error	40.150s	241.786us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.260m	15.065ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.891m	29.463ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.878m	14.910ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.986m	11.599ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.541m	15.256ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.746m	15.608ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.094m	15.619ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.296m	14.842ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	30.720s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	33.670s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	30.900s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	32.960s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	31.360s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.610s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.630s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	27.730s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.800s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.440s	10.360us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	27.380s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	28.840s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.060s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	27.320s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.730s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.650s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.210s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.150s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.680s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.900s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.150s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.330s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.380s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.520s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.730s	10.380us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.083m	11.418ms	1	1	100.00
		rom_e2e_asm_init_dev	38.237m	16.160ms	1	1	100.00
		rom_e2e_asm_init_prod	37.172m	14.956ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.761m	14.965ms	1	1	100.00
		rom_e2e_asm_init_rma	37.684m	14.749ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.361m	14.713ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.141m	15.362ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.884m	15.239ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.790m	15.380ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.784m	35.010ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.784m	35.010ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.938m	3.206ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.994m	3.201ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.916m	2.550ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.997m	2.766ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	28.764m	13.926ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.821m	3.147ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.577m	4.890ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	4.564m	4.667ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.841m	5.483ms	1	1	100.00
		chip_plic_all_irqs_10	4.183m	3.740ms	1	1	100.00
		chip_plic_all_irqs_20	6.177m	3.638ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.623m	3.383ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.701m	13.063ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.805m	4.038ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.707m	3.241ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.157m	10.772ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.455m	6.310ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.658m	8.971ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.000m	8.093ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.912h	255.760ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.635m	3.970ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.401m	6.211ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.635m	3.970ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.759m	8.909ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.759m	8.909ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.083m	7.121ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.751m	4.864ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.050m	5.819ms	1	1	100.00
		chip_sw_aes_idle	1.997m	2.766ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.000m	2.545ms	1	1	100.00
		chip_sw_kmac_idle	2.836m	2.398ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.691m	4.371ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.883m	4.536ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.022m	4.348ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.614m	4.066ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.936m	10.223ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.329m	4.250ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.708m	4.552ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.217m	4.144ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.791m	4.257ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.869m	4.540ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.936m	4.994ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.935m	7.595ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	7.102m	9.727ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.217m	4.144ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.791m	4.257ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.218m	3.987ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.459m	6.311ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.922m	17.465ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.994m	3.201ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.954m	7.040ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.415m	3.155ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.673m	13.189ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.576m	2.854ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.450m	4.117ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.885m	2.055ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.832m	2.315ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.843m	4.762ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.130m	7.292ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	47.944m	24.136ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.765m	3.367ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.484m	2.720ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	14.463m	9.963ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.621m	3.275ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.264m	4.835ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.243m	25.573ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	31.902m	17.158ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.935m	7.595ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.171m	4.595ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.621m	3.495ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	4.564m	4.667ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.455m	6.310ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	10.466m	5.504ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.719m	3.161ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.618m	5.227ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.550m	2.914ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.113h	26.201ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.888m	3.171ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.554m	7.365ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.888m	3.171ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	10.466m	5.504ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.298m	2.573ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.421m	19.033ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.944m	5.519ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.459m	6.311ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.686m	3.747ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.218m	3.987ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	51.170m	43.771ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.421m	19.033ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.926m	2.830ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.044m	8.929ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.078m	5.458ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	51.170m	43.771ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.078m	5.458ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.078m	5.458ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.078m	5.458ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.078m	5.458ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	4.564m	4.667ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.916m	7.654ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.384m	5.186ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.133m	4.905ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.133m	4.905ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.148m	2.568ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.415m	3.155ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.000m	2.545ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.174m	3.240ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	6.276m	4.045ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.842m	4.565ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.170m	5.059ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.617m	5.292ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.832m	3.941ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.044m	8.929ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.673m	13.189ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	27.775m	11.894ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	28.764m	13.926ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	33.563m	12.393ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.478m	3.172ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.663m	2.966ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.576m	2.854ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.044m	8.929ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	8.747m	11.147ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.109m	3.115ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	9.487m	6.046ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.836m	2.398ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.577m	4.890ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	10.094m	9.555ms	1	1	100.00
		chip_tap_straps_rma	10.985m	10.396ms	1	1	100.00
		chip_tap_straps_prod	1.597m	2.922ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.989m	2.356ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	8.747m	11.147ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	8.747m	11.147ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	8.747m	11.147ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	24.142m	11.685ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.078m	5.458ms	1	1	100.00
		chip_sw_flash_rma_unlocked	51.170m	43.771ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.087m	3.249ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.443m	5.281ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.973m	8.187ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.281m	8.321ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.747m	11.147ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.044m	8.929ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	6.645m	9.057ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.315m	7.655ms	1	1	100.00
		chip_prim_tl_access	2.916m	7.654ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	7.102m	9.727ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.329m	4.250ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.708m	4.552ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.217m	4.144ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.791m	4.257ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.869m	4.540ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.936m	4.994ms	1	1	100.00
		chip_tap_straps_dev	10.094m	9.555ms	1	1	100.00
		chip_tap_straps_rma	10.985m	10.396ms	1	1	100.00
		chip_tap_straps_prod	1.597m	2.922ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.482m	8.948ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.949m	3.994ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.404m	3.713ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.486m	4.007ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.502m	4.036ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	22.257m	34.457ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.482m	8.948ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.061h	48.599ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	58.037m	46.822ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.294m	10.670ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	59.823m	46.337ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	22.257m	34.457ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.199m	3.133ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.235m	2.979ms	1	1	100.00
		rom_volatile_raw_unlock	1.208m	2.906ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.159m	16.771ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.922m	17.465ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.050m	5.819ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.050m	5.819ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.050m	5.819ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.449m	3.184ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	8.747m	11.147ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.421m	19.033ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.449m	3.184ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.044m	8.929ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.776m	4.593ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.834m	3.146ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.421m	19.033ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.449m	3.184ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.044m	8.929ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.776m	4.593ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.834m	3.146ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	8.747m	11.147ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.918m	5.577ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.989m	2.356ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.087m	3.249ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.443m	5.281ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.973m	8.187ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.281m	8.321ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.747m	11.147ms	1	1	100.00
		chip_prim_tl_access	2.916m	7.654ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.916m	7.654ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.557m	9.582ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.523m	8.089ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	17.976m	27.000ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.720m	7.595ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.372m	7.353ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.739m	6.258ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	11.608m	23.244ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.237m	13.884ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	5.759m	8.909ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	15.419m	11.496ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.508m	5.160ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.523m	8.089ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.852m	4.938ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	30.132m	32.862ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.297m	7.816ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.998m	5.230ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.427m	20.588ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.698m	8.189ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	12.907m	8.782ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	17.739m	26.766ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.287m	2.824ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	4.564m	4.667ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.645m	9.057ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.645m	9.057ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	12.907m	8.782ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.427m	20.588ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.508m	5.160ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.401m	6.211ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.331m	3.749ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	2.979m	4.406ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.216m	4.682ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.701m	13.063ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.708m	2.217ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	4.564m	4.667ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	18.658m	8.971ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.413m	5.351ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.193m	5.439ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.270m	3.160ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.834m	3.146ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	2.979m	4.406ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	2.979m	4.406ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	10.375m	10.215ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.856m	14.342ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.331m	3.749ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.187m	5.332ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.041m	5.399ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	10.985m	10.396ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.482m	8.948ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.841m	5.483ms	1	1	100.00
		chip_plic_all_irqs_10	4.183m	3.740ms	1	1	100.00
		chip_plic_all_irqs_20	6.177m	3.638ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.351m	2.946ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.535m	2.571ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.260m	15.065ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.317m	7.147ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.341m	2.965ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.840m	3.041ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.709m	3.005ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.776m	4.593ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.450m	4.117ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	4.951m	8.718ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.358m	8.593ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.315m	7.655ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	4.564m	4.667ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.646m	4.977ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.698m	8.189ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.006m	24.043ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.220m	3.099ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.262m	3.675ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.174m	4.633ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.006m	24.043ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.006m	24.043ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	40.370m	21.067ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	40.370m	21.067ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.153m	6.487ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.784m	35.010ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.963m	2.482ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.221m	3.193ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.678m	4.290ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.727m	3.968ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.675m	7.922ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.308h	32.392ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.651m	12.072ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.751m	3.176ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	1.990m	2.780ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.461m	2.258ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.444h	71.235ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.379m	5.710ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.034m	11.401ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.207m	11.243ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.514m	11.734ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.901m	4.101ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.488m	5.050ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.155m	4.318ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	17.327s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.833m	5.356ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.370m	2.506ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	7.516m	3.728ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	18.721m	9.120ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.445m	2.179ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.941m	5.354ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.703m	2.106ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.797m	5.789ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.053m	5.574ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.182m	3.575ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	12.907m	8.782ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.034m	11.401ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.207m	11.243ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.514m	11.734ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.481m	4.213ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	4.564m	4.667ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.354h	37.784ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.354h	37.784ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.072m	3.580ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.624m	4.544ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	49.227m	18.730ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.293m	2.815ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.722m	5.882ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.361m	2.447ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.423m	3.425ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.278m	3.608ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.352s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.902m	3.509ms	1	1	100.00
		TOTAL			285	325	87.69

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.68690584577821849593976207207343419542190457754708554633062385392578087799354
    Line 592, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.9020324629589950634313741575670768962623775882496383809787754629513903555937
    Line 599, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.91546395822516660285361655484911776136753008742383042174234120787043705845043
    Line 741, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.31328826857348720447643400090445071509715801726845228691190613121859696486866
    Line 714, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.55293889557506992994338098001170134827597092194680483200060197650016062762368
    Line 644, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.44086853522170631791748225175306555451900572538943497621015264137106020155933
    Line 499, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.94736079670187979107079483138281538862770463009042596564760862713680045210230
    Line 562, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.102127869923701966519443864022892446021284247237547213916199323212737731449787
    Line 551, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.28896770962604594798249625657959308685456087011857857182907427835691881777327
    Line 559, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.50147525016285938599863151113910417023269213327111889423287111846220292179859
    Line 554, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 4 failures:

Test chip_sw_sleep_pwm_pulses has 1 failures.

0.chip_sw_sleep_pwm_pulses.5509471391310184804927517159003662454243209720497556744534747131663802508253
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:sleep_pwm_pulses_test_sim_dv".
  Building "//sw/device/tests:sleep_pwm_pulses_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=5509471391310184804927517159003662454243209720497556744534747131663802508253 //sw/device/tests:sleep_pwm_pulses_test_sim_dv
  2025/05/22 20:37:31 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
  Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
  FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 36

Test chip_sw_pattgen_ios has 1 failures.

0.chip_sw_pattgen_ios.114918367815890159489274826433702754041530591835002074529942018935079367058277
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pattgen_ios/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:pattgen_ios_test_sim_dv".
  Building "//sw/device/tests:pattgen_ios_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=114918367815890159489274826433702754041530591835002074529942018935079367058277 //sw/device/tests:pattgen_ios_test_sim_dv
  2025/05/22 20:37:31 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
  Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
  FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 36

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.96050479028090697291911460414980838364982553429922561052060337380706724279545
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.161s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.60341264236197398025283039010216446810661449953660666058521962754001415252311
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 7.520s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.92612591077773417373533459136618502069402461986504411296671575178260102494016
    Line 654, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.58022182557296226219210217444662363033349282764774713339197804729484360646423
    Line 656, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.89852309838441981084134881013973057052543148243077044433813864170673415303825
    Line 675, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.86318314505457168201284373668121596249347113656263651597795546141655266038260
    Line 730, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.20889748253704423680147812202297402819180316308637169172497921079125907180558
    Line 786, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.14878115252557545906544301958437558808673413404110948985008905841832305558416
    Line 745, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.68981975388419842641299734583180387967042522667790397491874111452100043650945
    Line 642, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.58221667256179098214766564200528847967608087545596820065992690113760123187708
    Line 710, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3206.000000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3206.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.75994466915109552986917840525365212041892798202235331483100106463447657002917
    Line 451, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2964.755132 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2964.755132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@82813) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.67734668656128465352182796832458209941475016833882393202378150770452308759877
Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4405.635400 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@82813) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4405.635400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.24048798809333673553476853295331637735282400425533408041330729548819332326835
    Line 441, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35009.693855 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35009.693855 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.82884584702521051191265255771526457758223746484622237575213884367991550631955
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3146.688050 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3146.688050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.109969502036180760144740870470075719924498650844591872230520838359725530667899
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3241.135960 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3241.135960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.111942851805150885482924310386056269950686646519813170312268602136414503223810
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3161.224278 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3161.224278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.15128013504308249128298814090013202735737921389027626955202184989711898665405
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3378.564000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3378.564000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.84807327506940946927701620305447728091912499806664137890291524227651939206971
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2699.700500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2699.700500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.66323010914092446075576616680809324600601034985807529852013611055731600633707
    Line 435, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 24632.488614 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 24632.488614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.71723236719922120402836443047519387883914967867078620100258967308454577201120
    Line 684, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.112189288113621411447818123880460842308413319476523162402777105869618230791281
    Line 670, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31857) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.83364895746710994445341557320377363782320512044167921652543406083873570153612
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2308.210618 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31857) { a_addr: 'h106f4  a_data: 'h13902df9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h4  a_user: 'h1b65f  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2308.210618 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---