ADC_CTRL Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.800s	5.936ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.380s	1.032ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.280s	404.364us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.149m	26.870ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.370s	647.986us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.780s	590.363us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.280s	404.364us	1	1	100.00
		adc_ctrl_csr_aliasing	2.370s	647.986us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.895m	168.812ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	3.306m	483.567ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	1.121m	163.860ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.505m	329.047ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	5.908m	445.284ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.316m	192.152ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.616m	166.901ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.611m	502.896ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.280s	5.302ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	13.700s	29.071ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	35.190s	74.456ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	8.831m	307.653ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.120s	461.451us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	357.141us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.250s	424.269us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.250s	424.269us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.380s	1.032ms	1	1	100.00
		adc_ctrl_csr_rw	2.280s	404.364us	1	1	100.00
		adc_ctrl_csr_aliasing	2.370s	647.986us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.930s	4.970ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.380s	1.032ms	1	1	100.00
		adc_ctrl_csr_rw	2.280s	404.364us	1	1	100.00
		adc_ctrl_csr_aliasing	2.370s	647.986us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.930s	4.970ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	5.000s	8.087ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.290s	9.513ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.290s	9.513ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	14.040s	87.274ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00