EDN Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.770s	26.525us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.710s	13.153us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.620s	23.634us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.270s	132.406us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.990s	35.284us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.780s	31.782us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.620s	23.634us	1	1	100.00
		edn_csr_aliasing	1.990s	35.284us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.060s	41.989us	1	1	100.00
V2	csrng_commands	edn_genbits	2.060s	41.989us	1	1	100.00
V2	genbits	edn_genbits	2.060s	41.989us	1	1	100.00
V2	interrupts	edn_intr	1.710s	33.305us	1	1	100.00
V2	alerts	edn_alert	1.830s	46.139us	1	1	100.00
V2	errs	edn_err	1.710s	156.322us	1	1	100.00
V2	disable	edn_disable	1.640s	61.406us	1	1	100.00
		edn_disable_auto_req_mode	1.910s	33.609us	1	1	100.00
V2	stress_all	edn_stress_all	3.750s	763.609us	1	1	100.00
V2	intr_test	edn_intr_test	1.610s	78.383us	1	1	100.00
V2	alert_test	edn_alert_test	1.810s	15.081us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.920s	61.331us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.920s	61.331us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.710s	13.153us	1	1	100.00
		edn_csr_rw	1.620s	23.634us	1	1	100.00
		edn_csr_aliasing	1.990s	35.284us	1	1	100.00
		edn_same_csr_outstanding	1.950s	36.209us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.710s	13.153us	1	1	100.00
		edn_csr_rw	1.620s	23.634us	1	1	100.00
		edn_csr_aliasing	1.990s	35.284us	1	1	100.00
		edn_same_csr_outstanding	1.950s	36.209us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.590s	507.552us	1	1	100.00
		edn_tl_intg_err	2.700s	289.483us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.650s	62.379us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.830s	46.139us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.590s	507.552us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.590s	507.552us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.590s	507.552us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.590s	507.552us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.830s	46.139us	1	1	100.00
		edn_sec_cm	6.590s	507.552us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.830s	46.139us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.700s	289.483us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	40.090s	2.046ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00