HMAC Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.960s 9.136ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.680s 43.158us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.800s 39.849us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.510s 377.428us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.110s 1.123ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.740s 53.032us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.800s 39.849us 1 1 100.00
hmac_csr_aliasing 5.110s 1.123ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 24.630s 7.708ms 1 1 100.00
V2 back_pressure hmac_back_pressure 18.080s 481.128us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.117m 6.494ms 1 1 100.00
hmac_test_sha384_vectors 5.903m 11.242ms 1 1 100.00
hmac_test_sha512_vectors 5.481m 21.936ms 1 1 100.00
hmac_test_hmac256_vectors 8.530s 1.014ms 1 1 100.00
hmac_test_hmac384_vectors 10.680s 342.053us 1 1 100.00
hmac_test_hmac512_vectors 10.450s 3.711ms 1 1 100.00
V2 burst_wr hmac_burst_wr 8.730s 3.438ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.528m 1.278ms 1 1 100.00
V2 error hmac_error 22.170s 6.964ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 18.650s 3.071ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.960s 9.136ms 1 1 100.00
hmac_long_msg 24.630s 7.708ms 1 1 100.00
hmac_back_pressure 18.080s 481.128us 1 1 100.00
hmac_datapath_stress 2.528m 1.278ms 1 1 100.00
hmac_burst_wr 8.730s 3.438ms 1 1 100.00
hmac_stress_all 3.519m 26.704ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.960s 9.136ms 1 1 100.00
hmac_long_msg 24.630s 7.708ms 1 1 100.00
hmac_back_pressure 18.080s 481.128us 1 1 100.00
hmac_datapath_stress 2.528m 1.278ms 1 1 100.00
hmac_wipe_secret 18.650s 3.071ms 1 1 100.00
hmac_test_sha256_vectors 3.117m 6.494ms 1 1 100.00
hmac_test_sha384_vectors 5.903m 11.242ms 1 1 100.00
hmac_test_sha512_vectors 5.481m 21.936ms 1 1 100.00
hmac_test_hmac256_vectors 8.530s 1.014ms 1 1 100.00
hmac_test_hmac384_vectors 10.680s 342.053us 1 1 100.00
hmac_test_hmac512_vectors 10.450s 3.711ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.960s 9.136ms 1 1 100.00
hmac_long_msg 24.630s 7.708ms 1 1 100.00
hmac_back_pressure 18.080s 481.128us 1 1 100.00
hmac_datapath_stress 2.528m 1.278ms 1 1 100.00
hmac_burst_wr 8.730s 3.438ms 1 1 100.00
hmac_error 22.170s 6.964ms 1 1 100.00
hmac_wipe_secret 18.650s 3.071ms 1 1 100.00
hmac_test_sha256_vectors 3.117m 6.494ms 1 1 100.00
hmac_test_sha384_vectors 5.903m 11.242ms 1 1 100.00
hmac_test_sha512_vectors 5.481m 21.936ms 1 1 100.00
hmac_test_hmac256_vectors 8.530s 1.014ms 1 1 100.00
hmac_test_hmac384_vectors 10.680s 342.053us 1 1 100.00
hmac_test_hmac512_vectors 10.450s 3.711ms 1 1 100.00
hmac_stress_all 3.519m 26.704ms 1 1 100.00
V2 stress_all hmac_stress_all 3.519m 26.704ms 1 1 100.00
V2 alert_test hmac_alert_test 1.490s 22.651us 1 1 100.00
V2 intr_test hmac_intr_test 1.510s 14.567us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.340s 713.877us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.340s 713.877us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.680s 43.158us 1 1 100.00
hmac_csr_rw 1.800s 39.849us 1 1 100.00
hmac_csr_aliasing 5.110s 1.123ms 1 1 100.00
hmac_same_csr_outstanding 2.330s 404.569us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.680s 43.158us 1 1 100.00
hmac_csr_rw 1.800s 39.849us 1 1 100.00
hmac_csr_aliasing 5.110s 1.123ms 1 1 100.00
hmac_same_csr_outstanding 2.330s 404.569us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.750s 202.477us 1 1 100.00
hmac_tl_intg_err 3.290s 774.079us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.290s 774.079us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.960s 9.136ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.500s 156.248us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.193m 10.027ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.730s 185.179us 1 1 100.00
TOTAL 28 28 100.00