I2C Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	21.990s	3.137ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	7.680s	648.338us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.420s	21.259us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.520s	32.928us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.100s	113.707us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.600s	225.705us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.940s	28.046us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.520s	32.928us	1	1	100.00
		i2c_csr_aliasing	2.600s	225.705us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.320s	246.872us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	3.887m	22.903ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	4.490s	379.328us	1	1	100.00
V2	host_override	i2c_host_override	1.600s	18.470us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.001m	2.915ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	51.400s	2.579ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.920s	737.408us	1	1	100.00
		i2c_host_fifo_fmt_empty	15.820s	1.703ms	1	1	100.00
		i2c_host_fifo_reset_rx	4.500s	221.885us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	41.770s	4.608ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.070s	2.810ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.900s	48.950us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.830s	4.597ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	5.097m	34.527ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.260s	798.102us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	35.960s	1.138ms	1	1	100.00
		i2c_target_intr_smoke	6.660s	1.102ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.320s	733.233us	1	1	100.00
		i2c_target_fifo_reset_tx	1.870s	179.957us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.700m	54.183ms	1	1	100.00
		i2c_target_stress_rd	35.960s	1.138ms	1	1	100.00
		i2c_target_intr_stress_wr	21.430s	12.431ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.980s	5.654ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	5.880s	4.344ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.590s	1.327ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	9.960s	10.377ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.610s	289.203us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.950s	435.606us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.490s	379.328us	1	1	100.00
		i2c_host_perf_precise	6.270s	719.283us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.070s	2.810ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.960s	305.660us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.560s	580.115us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.780s	2.064ms	1	1	100.00
		i2c_target_nack_txstretch	2.250s	2.910ms	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	9.970s	1.634ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.780s	1.988ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.470s	15.719us	1	1	100.00
V2	intr_test	i2c_intr_test	1.640s	49.122us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.270s	59.328us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.270s	59.328us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.420s	21.259us	1	1	100.00
		i2c_csr_rw	1.520s	32.928us	1	1	100.00
		i2c_csr_aliasing	2.600s	225.705us	1	1	100.00
		i2c_same_csr_outstanding	1.890s	22.727us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.420s	21.259us	1	1	100.00
		i2c_csr_rw	1.520s	32.928us	1	1	100.00
		i2c_csr_aliasing	2.600s	225.705us	1	1	100.00
		i2c_same_csr_outstanding	1.890s	22.727us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	2.160s	88.021us	1	1	100.00
		i2c_sec_cm	1.940s	50.994us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.160s	88.021us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	11.110s	884.972us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.790s	502.140us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	5.820s	863.968us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.44375305827730757109248957821423846484985171236894178187152151231741514974006
      Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 884971522 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 884971522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.87227493365204284605294248115044840511505189336257240695362223457087636436502
      Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 863967792 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 863967792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.5615561127118633718262947542926917408135133743280497357972928567386747304609
      Line 123, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 22902994424 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @2317712
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.3499554272277785243943694087077224348174345082049114986905755241988931612885
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 502139972 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 145 [0x91])
        UVM_INFO @ 502139972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.113137594064745756074560182431156427359859317744422958358415093565351284650577
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10377092626 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10377092626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.11920085568585781016563611223206707233593053111934354769370529348788330738706
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @  48949634 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x23941d14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @  48949634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.82136822335834410803154270870684818937426879752194196398616220774901586733672
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 2909973020 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 2909973020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---