KMAC/MASKED Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	3.190s	390.064us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.720s	40.922us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.710s	59.667us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	8.610s	2.024ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.240s	616.213us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.010s	128.385us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.710s	59.667us	1	1	100.00
		kmac_csr_aliasing	6.240s	616.213us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.870s	16.047us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.340s	39.137us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	17.540s	627.491us	1	1	100.00
V2	burst_write	kmac_burst_write	1.910m	2.194ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.188m	377.729ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.300s	4.780ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.780s	20.099ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.750s	1.338ms	1	1	100.00
		kmac_test_vectors_shake_128	39.652m	217.990ms	1	1	100.00
		kmac_test_vectors_shake_256	5.082m	37.989ms	1	1	100.00
		kmac_test_vectors_kmac	2.800s	94.192us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.850s	521.820us	1	1	100.00
V2	sideload	kmac_sideload	4.541m	11.262ms	1	1	100.00
V2	app	kmac_app	4.108m	11.573ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.822m	40.837ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.136m	39.032ms	1	1	100.00
V2	error	kmac_error	18.770s	4.676ms	1	1	100.00
V2	key_error	kmac_key_error	9.190s	8.547ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	8.480s	1.607ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	30.160s	507.777us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.190s	93.322us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	7.280s	515.891us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.980s	38.989us	1	1	100.00
V2	stress_all	kmac_stress_all	11.852m	141.912ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.600s	26.635us	1	1	100.00
V2	alert_test	kmac_alert_test	1.930s	27.050us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.520s	111.325us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.520s	111.325us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.720s	40.922us	1	1	100.00
		kmac_csr_rw	1.710s	59.667us	1	1	100.00
		kmac_csr_aliasing	6.240s	616.213us	1	1	100.00
		kmac_same_csr_outstanding	2.480s	63.486us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.720s	40.922us	1	1	100.00
		kmac_csr_rw	1.710s	59.667us	1	1	100.00
		kmac_csr_aliasing	6.240s	616.213us	1	1	100.00
		kmac_same_csr_outstanding	2.480s	63.486us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.630s	127.219us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.630s	127.219us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.630s	127.219us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.630s	127.219us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.950s	198.060us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.272m	20.191ms	1	1	100.00
		kmac_tl_intg_err	3.810s	526.616us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.810s	526.616us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.980s	38.989us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	3.190s	390.064us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.541m	11.262ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.630s	127.219us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.272m	20.191ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.272m	20.191ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.272m	20.191ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	3.190s	390.064us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.980s	38.989us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.272m	20.191ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	10.460s	302.248us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	3.190s	390.064us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.790s	1.556ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.102983120915489605716076367718529778001072009388649286923775953687362755323112
      Line 165, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1556282775 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1556282775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---