2214708| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 10.000s | 39.735us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 8.000s | 43.854us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 36.522us | 1 | 1 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 76.826us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 7.000s | 379.781us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 5.000s | 88.640us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 6.000s | 191.241us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 76.826us | 1 | 1 | 100.00 |
| otbn_csr_aliasing | 5.000s | 88.640us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 26.000s | 1.784ms | 1 | 1 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 14.000s | 722.764us | 1 | 1 | 100.00 |
| V1 | TOTAL | 9 | 9 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 22.000s | 1.341ms | 1 | 1 | 100.00 |
| V2 | multi_error | otbn_multi_err | 39.000s | 558.723us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 29.000s | 528.232us | 1 | 1 | 100.00 |
| V2 | stress_all | otbn_stress_all | 15.000s | 46.530us | 1 | 1 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 8.093s | 0 | 1 | 0.00 | |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 10.000s | 32.017us | 1 | 1 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 0.053s | 0 | 1 | 0.00 | |
| V2 | alert_test | otbn_alert_test | 7.000s | 55.022us | 1 | 1 | 100.00 |
| V2 | intr_test | otbn_intr_test | 5.000s | 11.876us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 7.000s | 165.264us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 7.000s | 165.264us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 36.522us | 1 | 1 | 100.00 |
| otbn_csr_rw | 6.000s | 76.826us | 1 | 1 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 88.640us | 1 | 1 | 100.00 | ||
| otbn_same_csr_outstanding | 11.000s | 22.336us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 36.522us | 1 | 1 | 100.00 |
| otbn_csr_rw | 6.000s | 76.826us | 1 | 1 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 88.640us | 1 | 1 | 100.00 | ||
| otbn_same_csr_outstanding | 11.000s | 22.336us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 9 | 11 | 81.82 | |||
| V2S | mem_integrity | otbn_imem_err | 11.000s | 37.773us | 1 | 1 | 100.00 |
| otbn_dmem_err | 9.000s | 32.786us | 1 | 1 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 9.000s | 107.001us | 1 | 1 | 100.00 |
| otbn_controller_ispr_rdata_err | 9.000s | 215.439us | 1 | 1 | 100.00 | ||
| otbn_mac_bignum_acc_err | 11.000s | 32.540us | 1 | 1 | 100.00 | ||
| otbn_urnd_err | 8.000s | 48.127us | 1 | 1 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 7.000s | 28.890us | 1 | 1 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 8.000s | 48.357us | 1 | 1 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 7.000s | 49.815us | 1 | 1 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| otbn_tl_intg_err | 16.000s | 109.058us | 1 | 1 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 33.000s | 223.927us | 1 | 1 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| V2S | prim_count_check | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 10.000s | 39.735us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 9.000s | 32.786us | 1 | 1 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 11.000s | 37.773us | 1 | 1 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 16.000s | 109.058us | 1 | 1 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 8.093s | 0 | 1 | 0.00 | |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 11.000s | 37.773us | 1 | 1 | 100.00 |
| otbn_dmem_err | 9.000s | 32.786us | 1 | 1 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 32.017us | 1 | 1 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 28.890us | 1 | 1 | 100.00 | ||
| otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 8.000s | 43.854us | 1 | 1 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 37.773us | 1 | 1 | 100.00 |
| otbn_dmem_err | 9.000s | 32.786us | 1 | 1 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 32.017us | 1 | 1 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 28.890us | 1 | 1 | 100.00 | ||
| otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 8.093s | 0 | 1 | 0.00 | |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 37.773us | 1 | 1 | 100.00 |
| otbn_dmem_err | 9.000s | 32.786us | 1 | 1 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 32.017us | 1 | 1 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 28.890us | 1 | 1 | 100.00 | ||
| otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 8.000s | 43.854us | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 9.000s | 33.405us | 1 | 1 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 9.000s | 216.768us | 1 | 1 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 14.000s | 188.878us | 1 | 1 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 14.000s | 188.878us | 1 | 1 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 8.000s | 43.976us | 1 | 1 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 17.000s | 102.245us | 1 | 1 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 9.000s | 41.667us | 1 | 1 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 9.000s | 41.667us | 1 | 1 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 10.000s | 51.092us | 0 | 1 | 0.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 8.000s | 43.854us | 1 | 1 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 8.000s | 43.854us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 8.000s | 43.854us | 1 | 1 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 29.000s | 528.232us | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 8.000s | 43.854us | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 8.000s | 43.854us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 11.000s | 132.308us | 1 | 1 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 8.000s | 43.854us | 1 | 1 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 11.000s | 36.596us | 0 | 1 | 0.00 |
| V2S | TOTAL | 18 | 20 | 90.00 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 3.250m | 1.231ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 36 | 41 | 87.80 |
Job returned non-zero exit code has 2 failures:
Test otbn_escalate has 1 failures.
0.otbn_escalate.106865880598629635963497422789302786763472813628280887095533297920223476922420
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest/run.log
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 106865880598629635963497422789302786763472813628280887095533297920223476922420 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_escalate.458438708 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_escalate.458438708 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=458438708 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_escalate_vseq -nowarn DSEM2009' seed=106865880598629635963497422789302786763472813628280887095533297920223476922420 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_escalate_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 106865880598629635963497422789302786763472813628280887095533297920223476922420 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest
2025/05/26 18:46:32 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
Test otbn_sw_errs_fatal_chk has 1 failures.
0.otbn_sw_errs_fatal_chk.81428354652908694698831374678524496564136876230500585437891945139389233337188
Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/run.log
[Executing]:
make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 81428354652908694698831374678524496564136876230500585437891945139389233337188 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_sw_errs_fatal_chk.2141688676 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_sw_errs_fatal_chk.2141688676 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=2141688676 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_sw_errs_fatal_chk_vseq -nowarn DSEM2009' seed=81428354652908694698831374678524496564136876230500585437891945139389233337188 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_sw_errs_fatal_chk_vseq
[make]: pre_run
mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest
cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 81428354652908694698831374678524496564136876230500585437891945139389233337188 --size 2000 --count 1 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/otbn-binaries
~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
0.otbn_stress_all_with_rand_reset.85486571838170976626445422756960975032036620913947851902020778091382782008170
Line 252, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1230995952 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1230995952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
0.otbn_sec_wipe_err.93436825793405299250511998002770301907893694392883084969582146403096735318553
Line 120, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 51092041 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 51092041 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 51092041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:
0.otbn_sec_cm.8602092422479842682683104336888121278138457022578882419799168505542063388288
Line 117, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 36596254 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 36596254 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR @ 36596254 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
UVM_INFO @ 36596254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---