PATTGEN Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: `2214708`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	27.886us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	28.118us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	14.095us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	1.366ms	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	81.571us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	48.350us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	14.095us	1	1	100.00
		pattgen_csr_aliasing	4.000s	81.571us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	3.267m	93.072ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	14.000s	1.901ms	1	1	100.00
V2	error	pattgen_error	4.000s	47.609us	1	1	100.00
V2	stress_all	pattgen_stress_all	2.700m	67.530ms	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	84.162us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	37.243us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	93.714us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	93.714us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	28.118us	1	1	100.00
		pattgen_csr_rw	4.000s	14.095us	1	1	100.00
		pattgen_csr_aliasing	4.000s	81.571us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	114.304us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	28.118us	1	1	100.00
		pattgen_csr_rw	4.000s	14.095us	1	1	100.00
		pattgen_csr_aliasing	4.000s	81.571us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	114.304us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	268.779us	1	1	100.00
		pattgen_sec_cm	4.000s	161.182us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	268.779us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	40.000s	1.876ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	30.000s	10.015ms	0	1	0.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 0.pattgen_inactive_level.49708998599885042595917724324837485362411640515088398846021758682964513944851
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10014525933 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x60c3f590, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10014525933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.49348959127268544245377961654637128204576543347589257467256955380766429782108
Line 119, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 840150524 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 840155805 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 840155805 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 840176007 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.87536489201358641733520155181352412595241808207077198587427599906599363824835
    Line 122, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 67530321486 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  --------------------------------------
  Name        Type          Size  Value
  --------------------------------------
  exp_item    pattgen_item  -     @11855
```