ROM_CTRL/32KB Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.110s 1.309ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.450s 542.041us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.880s 132.363us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.290s 184.895us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.210s 203.329us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.890s 1.499ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.880s 132.363us 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 203.329us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.190s 1.804ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.140s 170.275us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.910s 433.596us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 11.940s 2.503ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.940s 390.508us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.160s 125.206us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.720s 195.911us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.720s 195.911us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.450s 542.041us 1 1 100.00
rom_ctrl_csr_rw 4.880s 132.363us 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 203.329us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.540s 127.531us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.450s 542.041us 1 1 100.00
rom_ctrl_csr_rw 4.880s 132.363us 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 203.329us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.540s 127.531us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.225m 11.692ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 22.210s 1.752ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.545m 956.687us 1 1 100.00
rom_ctrl_tl_intg_err 23.930s 681.841us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.545m 956.687us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.545m 956.687us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.225m 11.692ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.225m 11.692ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.225m 11.692ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.225m 11.692ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.225m 11.692ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.545m 956.687us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.545m 956.687us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.110s 1.309ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.110s 1.309ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.110s 1.309ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 23.930s 681.841us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.225m 11.692ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.940s 390.508us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.225m 11.692ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.225m 11.692ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.225m 11.692ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 22.210s 1.752ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.545m 956.687us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.709m 1.749ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00