ROM_CTRL/64KB Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.200s 248.271us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.700s 615.908us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.740s 295.224us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.940s 298.381us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.470s 2.782ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.580s 225.444us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.740s 295.224us 1 1 100.00
rom_ctrl_csr_aliasing 6.470s 2.782ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.710s 1.803ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.840s 1.074ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.880s 412.299us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 24.280s 764.786us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.210s 1.424ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.210s 212.332us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.320s 2.393ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.320s 2.393ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.700s 615.908us 1 1 100.00
rom_ctrl_csr_rw 7.740s 295.224us 1 1 100.00
rom_ctrl_csr_aliasing 6.470s 2.782ms 1 1 100.00
rom_ctrl_same_csr_outstanding 7.420s 805.968us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.700s 615.908us 1 1 100.00
rom_ctrl_csr_rw 7.740s 295.224us 1 1 100.00
rom_ctrl_csr_aliasing 6.470s 2.782ms 1 1 100.00
rom_ctrl_same_csr_outstanding 7.420s 805.968us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.469m 1.989ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 24.770s 1.056ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.550m 3.512ms 1 1 100.00
rom_ctrl_tl_intg_err 36.790s 376.317us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.550m 3.512ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.550m 3.512ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.469m 1.989ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.469m 1.989ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.469m 1.989ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.469m 1.989ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.469m 1.989ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.550m 3.512ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.550m 3.512ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.200s 248.271us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.200s 248.271us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.200s 248.271us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 36.790s 376.317us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.469m 1.989ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.210s 1.424ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.469m 1.989ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.469m 1.989ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.469m 1.989ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 24.770s 1.056ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.550m 3.512ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.461m 13.132ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00