RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 4.280s 1.327ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.630s 316.812us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.650s 268.230us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 8.680s 3.292ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.770s 286.243us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 4.700s 3.116ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 6.660s 3.636ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 21.140s 13.522ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 40.340s 21.201ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.880s 656.806us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.870s 1.044ms 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.230s 321.952us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.060s 313.172us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.960s 214.248us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.830s 324.795us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.590s 75.935us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.570s 276.721us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.880s 656.806us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.680s 535.963us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.770s 340.834us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.230s 321.952us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.840s 162.857us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.400s 245.959us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 3.110s 92.355us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 26.090s 12.851ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 47.220s 3.418ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.480s 36.820us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 47.220s 3.418ms 1 1 100.00
rv_dm_csr_rw 3.110s 92.355us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.700s 55.457us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.760s 168.770us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 4.280s 1.327ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.820s 159.203us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.840s 178.814us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.730s 253.643us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.200s 925.962us 1 1 100.00
V2 sba rv_dm_sba_tl_access 14.130s 14.298ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.600s 97.660us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 4.050s 1.398ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.290s 492.910us 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.940s 256.095us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.290s 950.831us 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.780s 155.814us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.760s 389.474us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 16.790s 7.968ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.760s 33.541us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.570s 95.408us 1 1 100.00
V2 stress_all rv_dm_stress_all 14.520s 7.054ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.690s 58.860us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.800s 50.620us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.800s 50.620us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 47.220s 3.418ms 1 1 100.00
rv_dm_csr_hw_reset 2.400s 245.959us 1 1 100.00
rv_dm_csr_rw 3.110s 92.355us 1 1 100.00
rv_dm_same_csr_outstanding 4.040s 1.045ms 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 47.220s 3.418ms 1 1 100.00
rv_dm_csr_hw_reset 2.400s 245.959us 1 1 100.00
rv_dm_csr_rw 3.110s 92.355us 1 1 100.00
rv_dm_same_csr_outstanding 4.040s 1.045ms 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 1.980s 402.551us 1 1 100.00
rv_dm_tl_intg_err 9.900s 2.066ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 9.900s 2.066ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.290s 950.831us 1 1 100.00
rv_dm_debug_disabled 1.710s 85.000us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.290s 950.831us 1 1 100.00
rv_dm_debug_disabled 1.710s 85.000us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 4.280s 1.327ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.070s 143.498us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.840s 145.586us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.840s 145.586us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.070s 143.498us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.650s 128.305us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.640s 39.230us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets