RV_TIMER Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.510s	45.753us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.410s	27.971us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.440s	27.717us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.740s	190.245us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.660s	61.324us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.590s	16.640us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.440s	27.717us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	61.324us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	2.200s	286.794us	1	1	100.00
V2	disabled	rv_timer_disabled	1.710s	1.062ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.510s	287.280us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.510s	287.280us	1	1	100.00
V2	stress	rv_timer_stress_all	4.850s	5.560ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.540s	12.525us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.420s	14.692us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.040s	55.841us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.040s	55.841us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.410s	27.971us	1	1	100.00
		rv_timer_csr_rw	1.440s	27.717us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	61.324us	1	1	100.00
		rv_timer_same_csr_outstanding	1.790s	71.260us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.410s	27.971us	1	1	100.00
		rv_timer_csr_rw	1.440s	27.717us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	61.324us	1	1	100.00
		rv_timer_same_csr_outstanding	1.790s	71.260us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.650s	113.761us	1	1	100.00
		rv_timer_tl_intg_err	1.740s	50.237us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.740s	50.237us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	12.020s	14.939ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.550s	42.147us	1	1	100.00
		rv_timer_max	1.400s	14.558us	1	1	100.00
		TOTAL			19	19	100.00