SPI_DEVICE/1R1W Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.198m	53.399ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.850s	34.742us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.530s	80.719us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.220s	3.719ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.840s	909.447us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.270s	116.259us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.530s	80.719us	1	1	100.00
		spi_device_csr_aliasing	16.840s	909.447us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.470s	94.341us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.920s	41.306us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.800s	24.044us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.580s	1.244us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.620s	7.971us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.830s	740.671us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	6.830s	740.671us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.870s	311.759us	1	1	100.00
		spi_device_tpm_sts_read	1.540s	32.207us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	5.150s	3.467ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.910s	1.973ms	1	1	100.00
		spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.650s	647.262us	1	1	100.00
		spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.650s	647.262us	1	1	100.00
		spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.150s	173.795us	1	1	100.00
		spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.150s	173.795us	1	1	100.00
		spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.150s	173.795us	1	1	100.00
		spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.150s	173.795us	1	1	100.00
		spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.150s	173.795us	1	1	100.00
		spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.030s	625.932us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	25.620s	21.633ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	25.620s	21.633ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	25.620s	21.633ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.800s	585.790us	1	1	100.00
		spi_device_read_buffer_direct	8.400s	1.963ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	25.620s	21.633ms	1	1	100.00
		spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.308m	113.453ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.450s	103.115us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.450s	103.115us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.198m	53.399ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	50.010s	3.643ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.770s	66.001us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.530s	11.253us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.600s	96.312us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.500s	312.859us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.500s	312.859us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.850s	34.742us	1	1	100.00
		spi_device_csr_rw	2.530s	80.719us	1	1	100.00
		spi_device_csr_aliasing	16.840s	909.447us	1	1	100.00
		spi_device_same_csr_outstanding	3.580s	226.491us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.850s	34.742us	1	1	100.00
		spi_device_csr_rw	2.530s	80.719us	1	1	100.00
		spi_device_csr_aliasing	16.840s	909.447us	1	1	100.00
		spi_device_same_csr_outstanding	3.580s	226.491us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.040s	707.528us	1	1	100.00
		spi_device_tl_intg_err	11.880s	2.738ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.880s	2.738ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	52.440s	33.282ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.105450491952104449203746817917662733742243848358877731247690320985705561247017
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    844060 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[40])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    844060 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    844060 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[936])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.72913426599307186633781870572050050341312738213132197808299428095836408473123
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   5568543 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2d9eae [1011011001111010101110] vs 0x0 [0])
        UVM_ERROR @   5649543 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x98bcb0 [100110001011110010110000] vs 0x0 [0])
        UVM_ERROR @   5724543 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb2bcf6 [101100101011110011110110] vs 0x0 [0])
        UVM_ERROR @   5755543 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2c0731 [1011000000011100110001] vs 0x0 [0])
        UVM_ERROR @   5808543 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x813167 [100000010011000101100111] vs 0x0 [0])