SPI_DEVICE/2P Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 37.520s 6.432ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.860s 20.666us 1 1 100.00
V1 csr_rw spi_device_csr_rw 2.430s 113.224us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 16.200s 704.086us 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 6.430s 1.230ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.990s 60.623us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.430s 113.224us 1 1 100.00
spi_device_csr_aliasing 6.430s 1.230ms 1 1 100.00
V1 mem_walk spi_device_mem_walk 1.510s 116.986us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.350s 90.636us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 1.720s 16.125us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.820s 18.052us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 1.730s 42.527us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 1.750s 116.648us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 1.750s 116.648us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 4.180s 1.187ms 1 1 100.00
spi_device_tpm_sts_read 1.750s 48.458us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 11.160s 4.456ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 2.720s 1.418ms 1 1 100.00
spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 6.870s 1.433ms 1 1 100.00
spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 6.870s 1.433ms 1 1 100.00
spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 3.970s 2.030ms 1 1 100.00
spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 3.970s 2.030ms 1 1 100.00
spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 3.970s 2.030ms 1 1 100.00
spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 3.970s 2.030ms 1 1 100.00
spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 3.970s 2.030ms 1 1 100.00
spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 3.260s 420.930us 1 1 100.00
V2 mailbox_command spi_device_mailbox 10.840s 1.281ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 10.840s 1.281ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 10.840s 1.281ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 10.430s 13.727ms 1 1 100.00
spi_device_read_buffer_direct 7.170s 2.538ms 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 10.840s 1.281ms 1 1 100.00
spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 quad_spi spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 dual_spi spi_device_flash_all 1.240m 34.536ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 4.710s 470.160us 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 4.710s 470.160us 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 37.520s 6.432ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 34.080s 2.444ms 1 1 100.00
V2 stress_all spi_device_stress_all 3.971m 151.645ms 1 1 100.00
V2 alert_test spi_device_alert_test 1.650s 36.726us 1 1 100.00
V2 intr_test spi_device_intr_test 1.610s 45.251us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.810s 421.648us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.810s 421.648us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.860s 20.666us 1 1 100.00
spi_device_csr_rw 2.430s 113.224us 1 1 100.00
spi_device_csr_aliasing 6.430s 1.230ms 1 1 100.00
spi_device_same_csr_outstanding 3.850s 611.916us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.860s 20.666us 1 1 100.00
spi_device_csr_rw 2.430s 113.224us 1 1 100.00
spi_device_csr_aliasing 6.430s 1.230ms 1 1 100.00
spi_device_same_csr_outstanding 3.850s 611.916us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 2.090s 39.334us 1 1 100.00
spi_device_tl_intg_err 5.410s 390.749us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 5.410s 390.749us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 2.665m 84.959ms 1 1 100.00
TOTAL 33 33 100.00