SRAM_CTRL/MAIN Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	22.670s	3.401ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.610s	20.211us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.530s	11.929us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.140s	28.852us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.440s	27.135us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.940s	367.110us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.530s	11.929us	1	1	100.00
		sram_ctrl_csr_aliasing	1.440s	27.135us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.138m	93.956ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.811m	20.862ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.750m	32.320ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.662m	26.150ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	25.211m	488.833ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.602m	3.686ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	42.440s	38.573ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.810m	105.538ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.640s	2.531ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.068m	7.601ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	5.870s	976.832us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	28.680s	2.964ms	1	1	100.00
		sram_ctrl_throughput_w_readback	51.380s	3.972ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.062m	20.305ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.160s	1.528ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	21.007m	70.250ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.550s	16.167us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.800s	76.582us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.800s	76.582us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.610s	20.211us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	11.929us	1	1	100.00
		sram_ctrl_csr_aliasing	1.440s	27.135us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.790s	64.473us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.610s	20.211us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	11.929us	1	1	100.00
		sram_ctrl_csr_aliasing	1.440s	27.135us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.790s	64.473us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	32.810s	29.386ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.450s	2.258us	0	1	0.00
		sram_ctrl_tl_intg_err	2.220s	151.007us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.450s	2.258us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.220s	151.007us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.062m	20.305ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.062m	20.305ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.530s	11.929us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.810m	105.538ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.810m	105.538ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.810m	105.538ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	42.440s	38.573ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.350s	684.378us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	32.810s	29.386ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.660s	1.341ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	22.670s	3.401ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	22.670s	3.401ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.810m	105.538ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.450s	2.258us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	42.440s	38.573ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.450s	2.258us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.450s	2.258us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	22.670s	3.401ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.450s	2.258us	0	1	0.00
V2S		TOTAL			2	5	40.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.680s	1.774ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.52775110753255465856021825574905031372769431866005322242917664687856085666910
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1341443200 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x5e) != exp (0x35)
        UVM_INFO @ 1341443200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.1872902279302025816519490454042889630162213326456840545710630880574324128085
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 684378134 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 684378134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.58634517173856851481273729160601475952576021817298516873559227475953182951503
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2258330 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2258330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---