SRAM_CTRL/RET Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.750s	925.305us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.600s	23.914us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.590s	27.926us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.700s	257.039us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.140s	15.461us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.180s	68.943us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.590s	27.926us	1	1	100.00
		sram_ctrl_csr_aliasing	2.140s	15.461us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.460s	824.649us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.210s	45.030us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.978m	21.556ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.739m	19.638ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.830s	1.137ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	13.790s	310.317us	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.300s	65.323us	1	1	100.00
V2	executable	sram_ctrl_executable	43.980s	654.538us	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.370s	3.955ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.745m	91.405ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	6.390s	66.132us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	2.340s	83.659us	1	1	100.00
		sram_ctrl_throughput_w_readback	5.270s	1.160ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.941m	48.317ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.720s	74.732us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	28.530m	73.327ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.500s	24.708us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.410s	403.589us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.410s	403.589us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.600s	23.914us	1	1	100.00
		sram_ctrl_csr_rw	1.590s	27.926us	1	1	100.00
		sram_ctrl_csr_aliasing	2.140s	15.461us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	24.309us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.600s	23.914us	1	1	100.00
		sram_ctrl_csr_rw	1.590s	27.926us	1	1	100.00
		sram_ctrl_csr_aliasing	2.140s	15.461us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	24.309us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.570s	886.222us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.570s	1.845us	0	1	0.00
		sram_ctrl_tl_intg_err	2.870s	256.273us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.570s	1.845us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.870s	256.273us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.941m	48.317ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.941m	48.317ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.590s	27.926us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	43.980s	654.538us	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	43.980s	654.538us	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	43.980s	654.538us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.300s	65.323us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.790s	74.142us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.570s	886.222us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.560s	23.977us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.750s	925.305us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.750s	925.305us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	43.980s	654.538us	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.570s	1.845us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.300s	65.323us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.570s	1.845us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.570s	1.845us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.750s	925.305us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.570s	1.845us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.289m	5.943ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.113098007606454566686240696198506614634085793395454033229897643073347774890622
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  23977113 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x9) != exp (0x3e)
        UVM_INFO @  23977113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.1865007815957900398885802838067164355145638328795806526196640601049604868051
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1845117 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1845117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---