SYSRST_CTRL Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 3.830s 2.120ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 3.220s 2.474ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.630s 2.436ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.840s 2.505ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 4.450s 4.050ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.080s 2.343ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 2.392m 39.132ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 5.040s 2.697ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.120s 2.036ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.080s 2.343ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.040s 2.697ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 2.784m 165.086ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 47.680s 28.079ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 4.520s 3.153ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 4.340s 2.827ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.180s 2.515ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.740s 2.081ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 7.960s 3.243ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.550s 2.642ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 3.610s 5.417ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 30.440s 29.205ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 22.930s 11.370ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.930s 2.018ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.590s 2.042ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 6.320s 2.031ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 6.320s 2.031ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 4.450s 4.050ms 1 1 100.00
sysrst_ctrl_csr_rw 2.080s 2.343ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.040s 2.697ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.080s 4.779ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 4.450s 4.050ms 1 1 100.00
sysrst_ctrl_csr_rw 2.080s 2.343ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.040s 2.697ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.080s 4.779ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.332m 42.011ms 1 1 100.00
sysrst_ctrl_tl_intg_err 50.120s 22.221ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 50.120s 22.221ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 7.270s 6.212ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00