UART Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: 2214708

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	18.310s	5.652ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.600s	51.602us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.440s	23.344us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.890s	1.659ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.650s	31.164us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.910s	28.050us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.440s	23.344us	1	1	100.00
		uart_csr_aliasing	1.650s	31.164us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	22.830s	35.747ms	1	1	100.00
V2	parity	uart_smoke	18.310s	5.652ms	1	1	100.00
		uart_tx_rx	22.830s	35.747ms	1	1	100.00
V2	parity_error	uart_intr	2.888m	326.847ms	1	1	100.00
		uart_rx_parity_err	28.290s	94.234ms	1	1	100.00
V2	watermark	uart_tx_rx	22.830s	35.747ms	1	1	100.00
		uart_intr	2.888m	326.847ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.139m	205.191ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	21.710s	41.260ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	19.420s	18.160ms	1	1	100.00
V2	rx_frame_err	uart_intr	2.888m	326.847ms	1	1	100.00
V2	rx_break_err	uart_intr	2.888m	326.847ms	1	1	100.00
V2	rx_timeout	uart_intr	2.888m	326.847ms	1	1	100.00
V2	perf	uart_perf	7.094m	33.475ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.990s	3.759ms	1	1	100.00
V2	line_loopback	uart_loopback	5.990s	3.759ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	29.210s	479.369ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	13.110s	42.012ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	4.360s	1.320ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	36.830s	5.261ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.629m	295.493ms	1	1	100.00
V2	stress_all	uart_stress_all	1.648m	220.456ms	1	1	100.00
V2	alert_test	uart_alert_test	1.610s	11.449us	1	1	100.00
V2	intr_test	uart_intr_test	1.800s	34.849us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.060s	289.586us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.060s	289.586us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.600s	51.602us	1	1	100.00
		uart_csr_rw	1.440s	23.344us	1	1	100.00
		uart_csr_aliasing	1.650s	31.164us	1	1	100.00
		uart_same_csr_outstanding	1.520s	68.432us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.600s	51.602us	1	1	100.00
		uart_csr_rw	1.440s	23.344us	1	1	100.00
		uart_csr_aliasing	1.650s	31.164us	1	1	100.00
		uart_same_csr_outstanding	1.520s	68.432us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.780s	137.419us	1	1	100.00
		uart_tl_intg_err	1.870s	47.271us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.870s	47.271us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	19.300s	2.582ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00