CHIP Simulation Results

Monday May 26 2025 18:33:00 UTC

GitHub Revision: `2214708`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.202m	2.922ms	1	1	100.00
		chip_sw_example_rom	1.091m	3.087ms	1	1	100.00
		chip_sw_example_manufacturer	1.499m	2.856ms	1	1	100.00
		chip_sw_example_concurrency	2.441m	3.446ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.509m	5.287ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.927m	3.905ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.870m	5.974ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	53.088m	28.798ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	4.558m	7.716ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	53.088m	28.798ms	1	1	100.00
		chip_csr_rw	2.927m	3.905ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.590s	49.612us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.531m	4.545ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.531m	4.545ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.531m	4.545ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.134m	4.625ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.134m	4.625ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.311m	3.619ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.650m	4.852ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.456m	3.824ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.611m	4.420ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	27.824m	12.740ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	17.502m	12.994ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.912m	4.719ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.912m	4.719ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.929m	2.912ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.327m	3.612ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.050m	3.524ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.039m	3.198ms	1	1	100.00
		chip_tap_straps_testunlock0	1.906m	3.188ms	1	1	100.00
		chip_tap_straps_rma	3.647m	5.369ms	1	1	100.00
		chip_tap_straps_prod	1.697m	2.336ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.646m	2.467ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.540m	8.111ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.561m	5.706ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.561m	5.706ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.042m	8.113ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	26.201m	18.129ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.476m	4.049ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.903m	5.841ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.140m	18.194ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.950m	3.300ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.923m	6.581ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.003m	3.435ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.228m	8.623ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.653m	2.496ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.218m	4.398ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.528m	3.400ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.836m	2.979ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.601m	6.971ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.828m	4.775ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.056m	3.250ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.828m	4.775ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.013m	3.228ms	1	1	100.00
		chip_sw_aes_smoketest	2.165m	2.279ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.387m	3.133ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.302m	2.862ms	1	1	100.00
		chip_sw_csrng_smoketest	2.414m	2.828ms	1	1	100.00
		chip_sw_entropy_src_smoketest	5.386m	4.535ms	1	1	100.00
		chip_sw_gpio_smoketest	2.538m	3.141ms	1	1	100.00
		chip_sw_hmac_smoketest	3.563m	3.304ms	1	1	100.00
		chip_sw_kmac_smoketest	2.605m	2.924ms	1	1	100.00
		chip_sw_otbn_smoketest	11.692m	7.167ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.206m	4.796ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.620m	5.754ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.702m	3.404ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.603m	2.977ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.868m	2.764ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.442m	2.544ms	1	1	100.00
		chip_sw_uart_smoketest	1.889m	2.834ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.638m	2.955ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.242m	4.514ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.980h	60.545ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.866m	15.815ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.381m	4.434ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.322m	2.924ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.840m	2.860ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.812h	52.716ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.905h	57.200ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.721m	3.631ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.721m	3.631ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	53.088m	28.798ms	1	1	100.00
		chip_same_csr_outstanding	15.355m	14.170ms	1	1	100.00
		chip_csr_hw_reset	2.509m	5.287ms	1	1	100.00
		chip_csr_rw	2.927m	3.905ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	53.088m	28.798ms	1	1	100.00
		chip_same_csr_outstanding	15.355m	14.170ms	1	1	100.00
		chip_csr_hw_reset	2.509m	5.287ms	1	1	100.00
		chip_csr_rw	2.927m	3.905ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	8.170s	229.158us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.240s	52.813us	1	1	100.00
		xbar_smoke_large_delays	38.360s	6.565ms	1	1	100.00
		xbar_smoke_slow_rsp	41.170s	4.673ms	1	1	100.00
		xbar_random_zero_delays	23.430s	423.557us	1	1	100.00
		xbar_random_large_delays	3.210m	34.333ms	1	1	100.00
		xbar_random_slow_rsp	1.244m	9.147ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	16.190s	226.376us	1	1	100.00
		xbar_error_and_unmapped_addr	11.880s	231.556us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	20.320s	410.245us	1	1	100.00
		xbar_error_and_unmapped_addr	11.880s	231.556us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	38.090s	1.329ms	1	1	100.00
		xbar_access_same_device_slow_rsp	8.409m	62.806ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	35.050s	2.209ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.932m	4.738ms	1	1	100.00
		xbar_stress_all_with_error	2.114m	6.738ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	35.110s	144.282us	1	1	100.00
		xbar_stress_all_with_reset_error	2.773m	1.821ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.866m	15.815ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.076m	29.135ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.387m	15.526ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.145m	11.538ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.866m	15.358ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.410m	15.728ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.970m	15.795ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.927m	14.909ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.060s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	29.880s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	28.800s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	30.140s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	31.770s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.370s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.810s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	29.510s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.510s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.790s	10.240us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	24.990s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.580s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.600s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.290s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.000s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.660s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.430s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.580s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	27.270s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.380s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.390s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	27.170s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	28.280s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	27.000s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	27.010s	10.400us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.872m	11.097ms	1	1	100.00
		rom_e2e_asm_init_dev	36.627m	15.935ms	1	1	100.00
		rom_e2e_asm_init_prod	38.497m	15.597ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.342m	15.511ms	1	1	100.00
		rom_e2e_asm_init_rma	34.837m	14.639ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.484m	14.445ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	34.907m	14.577ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.366m	14.776ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.084m	15.747ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.393m	34.776ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.393m	34.776ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.436m	2.668ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.950m	3.300ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.933m	3.235ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.336m	2.588ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	22.080m	10.360ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.361m	3.089ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.042m	4.161ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	4.573m	5.840ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.531m	5.523ms	1	1	100.00
		chip_plic_all_irqs_10	3.427m	3.298ms	1	1	100.00
		chip_plic_all_irqs_20	5.585m	4.635ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.881m	2.893ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.137m	15.478ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.191m	3.913ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.087m	2.647ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.339m	11.727ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	9.340m	4.683ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.634m	6.504ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.865m	7.761ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.876h	256.092ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.653m	3.575ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.206m	4.796ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.653m	3.575ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.140m	6.611ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.140m	6.611ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.184m	7.780ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.326m	5.489ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.618m	6.283ms	1	1	100.00
		chip_sw_aes_idle	2.336m	2.588ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.203m	2.511ms	1	1	100.00
		chip_sw_kmac_idle	2.183m	2.098ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.694m	5.291ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.704m	5.060ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.280m	5.253ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.165m	4.393ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.072m	10.451ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.723m	4.109ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.895m	4.743ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.052m	3.915ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.362m	4.565ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.920m	3.525ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.800m	5.122ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.042m	8.113ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.807m	5.386ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.052m	3.915ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.362m	4.565ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.476m	4.049ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.903m	5.841ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.140m	18.194ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.950m	3.300ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.923m	6.581ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.003m	3.435ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.228m	8.623ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.653m	2.496ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.218m	4.398ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.528m	3.400ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.869m	1.998ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.534m	4.190ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.054m	6.834ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.075m	24.376ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.302m	2.769ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.346m	2.853ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.782m	8.087ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.806m	3.404ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.272m	4.005ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.414m	19.409ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	23.894m	13.700ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.042m	8.113ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.235m	4.392ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.727m	2.793ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	4.573m	5.840ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	9.340m	4.683ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.478m	5.987ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.759m	2.817ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.591m	7.121ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.959m	2.421ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.207h	30.245ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.145m	2.620ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.448m	7.018ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.145m	2.620ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.478m	5.987ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.995m	2.853ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	16.976m	23.986ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.545m	5.455ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.903m	5.841ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.538m	3.241ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.476m	4.049ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	56.775m	43.334ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	16.976m	23.986ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.265m	2.923ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	24.106m	11.787ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.697m	4.330ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	56.775m	43.334ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.697m	4.330ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.697m	4.330ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.697m	4.330ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.697m	4.330ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	4.573m	5.840ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.619m	6.328ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.430m	5.298ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.107m	6.171ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.107m	6.171ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.101m	2.626ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.003m	3.435ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.203m	2.511ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.995m	3.603ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.957m	4.814ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.974m	5.500ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.689m	4.544ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.192m	4.532ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.174m	4.040ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	24.106m	11.787ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.228m	8.623ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	26.342m	12.499ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	22.080m	10.360ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	32.207m	11.181ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.073m	2.353ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.295m	3.082ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.653m	2.496ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	24.106m	11.787ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	7.148m	11.120ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.424m	2.859ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.278m	4.834ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.183m	2.098ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.042m	4.161ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.039m	3.198ms	1	1	100.00
		chip_tap_straps_rma	3.647m	5.369ms	1	1	100.00
		chip_tap_straps_prod	1.697m	2.336ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.996m	2.256ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	7.148m	11.120ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	7.148m	11.120ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	7.148m	11.120ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	23.942m	12.019ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.697m	4.330ms	1	1	100.00
		chip_sw_flash_rma_unlocked	56.775m	43.334ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.136m	2.808ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.022m	6.792ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.816m	5.774ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.832m	6.075ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.148m	11.120ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.106m	11.787ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.653m	8.791ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.393m	10.097ms	1	1	100.00
		chip_prim_tl_access	1.619m	6.328ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.807m	5.386ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.723m	4.109ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.895m	4.743ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.052m	3.915ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.362m	4.565ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.920m	3.525ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.800m	5.122ms	1	1	100.00
		chip_tap_straps_dev	2.039m	3.198ms	1	1	100.00
		chip_tap_straps_rma	3.647m	5.369ms	1	1	100.00
		chip_tap_straps_prod	1.697m	2.336ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.547m	12.584ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.807m	3.808ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.667m	3.590ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.509m	2.428ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	32.660m	27.749ms	0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.347m	30.132ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.547m	12.584ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	58.624m	50.084ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.130h	50.590ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	10.531m	10.313ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	59.951m	46.616ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.347m	30.132ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.400m	2.750ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.366m	2.411ms	1	1	100.00
		rom_volatile_raw_unlock	1.125m	2.932ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.937m	16.598ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.140m	18.194ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.618m	6.283ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.618m	6.283ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.618m	6.283ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.895m	3.668ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	7.148m	11.120ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	16.976m	23.986ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.895m	3.668ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.106m	11.787ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.664m	5.229ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.059m	3.149ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	16.976m	23.986ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.895m	3.668ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.106m	11.787ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.664m	5.229ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.059m	3.149ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	7.148m	11.120ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.556m	4.088ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.996m	2.256ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.136m	2.808ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.022m	6.792ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.816m	5.774ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.832m	6.075ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.148m	11.120ms	1	1	100.00
		chip_prim_tl_access	1.619m	6.328ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.619m	6.328ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.622m	9.903ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	6.264m	8.249ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.775m	23.806ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.062m	7.144ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.272m	9.464ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.109m	7.306ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.239m	25.292ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.798m	14.888ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.140m	6.611ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.553m	10.420ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.979m	4.384ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	6.264m	8.249ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.037m	4.126ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	42.121m	41.611ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.256m	5.600ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.412m	5.097ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.287m	27.718ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.578m	5.787ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	18.266m	13.335ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	27.579m	26.890ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.325m	3.095ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	4.573m	5.840ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.653m	8.791ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.653m	8.791ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	18.266m	13.335ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.287m	27.718ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.979m	4.384ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.206m	4.796ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	2.748m	2.866ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	2.881m	3.933ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.535m	3.555ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.137m	15.478ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.850m	3.006ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	4.573m	5.840ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	12.634m	6.504ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.437m	4.862ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.588m	4.397ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.056m	3.073ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.059m	3.149ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	2.881m	3.933ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	2.881m	3.933ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.065m	3.935ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.201m	13.656ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	2.748m	2.866ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.670m	3.146ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.185m	5.631ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.647m	5.369ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.547m	12.584ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.531m	5.523ms	1	1	100.00
		chip_plic_all_irqs_10	3.427m	3.298ms	1	1	100.00
		chip_plic_all_irqs_20	5.585m	4.635ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.246m	2.370ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.443m	2.763ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.866m	15.815ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.014m	7.817ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.776m	2.675ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.303m	3.708ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.452m	3.654ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.664m	5.229ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.218m	4.398ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.793m	8.971ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.950m	7.895ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.393m	10.097ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	4.573m	5.840ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.561m	5.706ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.578m	5.787ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.693m	21.019ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.272m	2.874ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.784m	4.179ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.042m	4.023ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.693m	21.019ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.693m	21.019ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	37.091m	20.963ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	37.091m	20.963ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.612m	6.058ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.393m	34.776ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.948m	2.487ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.409m	3.127ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.146m	2.956ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.178m	4.415ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.687m	8.263ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.366h	31.531ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.889m	11.949ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.218m	2.769ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.708m	3.355ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.733m	3.031ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.435h	71.546ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.275m	6.058ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.664m	11.482ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.439m	12.194ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.779m	10.768ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.763m	4.283ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.981m	3.098ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.504m	4.690ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.862s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.774m	4.858ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.833m	2.676ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.304m	4.737ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	19.742m	9.475ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.537m	2.320ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.002m	5.279ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.885m	2.922ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.590m	4.926ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.906m	6.321ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.122m	4.492ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	18.266m	13.335ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.664m	11.482ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.439m	12.194ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.779m	10.768ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.806m	5.751ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	4.573m	5.840ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.372h	38.952ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.372h	38.952ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.182m	3.099ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.134m	4.625ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	47.937m	18.863ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.464m	2.861ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.658m	6.198ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.750m	3.185ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.034m	3.516ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	2.648m	3.314ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.898s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.482m	3.022ms	1	1	100.00
		TOTAL			284	325	87.38

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.102844261261420571250655634813034051094519296937571666703796555135698488214420
    Line 656, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.85319538088764771018799348163994305852566367123292862970429175283257203582084
    Line 699, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.99969602079026214940499959806734264828883723103764488860019671650502966453265
    Line 658, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.115329735524337362992428929158158768182424444473128054625096215785454548038139
    Line 616, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.57321209354737323511247213173445156205840008804349850347874595483681673686503
    Line 670, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.107101498394695016102345877501543034839758846584753367680518536598135422950388
    Line 488, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.52712703239808682906489034480154432508229932735667131624737001006802555142681
    Line 542, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.115751128847249473148678562284935657252314226065251725455264684886479978446439
    Line 564, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.20053832730240966090360818622184613303882465867706533098068582630519631229524
    Line 571, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.28920317304049651596079750495222308961743007515861010040403310721443283170545
    Line 589, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.15941597657658243475083820177143209321640218332837428657603206129319810414717
    Line 759, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.35559197404875762077996611419241062966887593050064683460171358669839706163896
    Line 702, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.63858524653500456729781761869978380702173083936046976202564516958472309898197
    Line 686, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.54920759322711417515026638375690015187033027951022655427772144531250620846027
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.162s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.20124370676202407960131931864608592450370435072664957472192879969390738270289
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.582s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.12121976542293106952776513322631731968863966748296069412667465284449961054632
    Line 878, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.56777706734925085765242107116478662146588171835938881483778750607910493616101
    Line 635, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.75239289225336812181633558842299981129043031326208419118007353239538370904248
    Line 747, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.10783243579433096851649150525156774422550171648595936484063434480842761031346
    Line 637, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.76581521518861934281014571485844076760487387536379876221011831105880797810583
    Line 436, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2675.338720 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2675.338720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:820) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_rand_to_scrap.4667763979501503987078117415240647251369196116690060762079881934817115301039
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_FATAL @ 27748.768380 us: (chip_sw_base_vseq.sv:820) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!
  UVM_INFO @ 27748.768380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78349) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.98174325360708321741498240025456999916767587902271699697247524394668723016938
Line 452, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3932.894584 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78349) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3932.894584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.94729929038888427048961163120618473590474613447205872100779230928094247828521
    Line 435, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34775.715527 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34775.715527 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.75263628345522271189429614514816308837388948736397419620168538662966665585126
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3088.641286 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert 52!
  UVM_INFO @ 3088.641286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.29083487528864675214009028045943971664256704203304263378884037092790508541214
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2647.253610 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2647.253610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.17879500983506993885303319358559466143927875029984399830798134907943123495695
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2817.248072 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2817.248072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@268533) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.98727812829555233374979284531668342445393359022626038410887451269654819093418
Line 220, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3630.825768 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@268533) { a_addr: 'h106b8  a_data: 'h5158e0ac  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h4  a_user: 'h18698  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3630.825768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.33874236951005591507651853650534131927648740775933983991972839902087468255758
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3313.624120 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3313.624120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.75982371234421316531990527236980291085025120715345656533950970160574005290467
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 3030.853116 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 3030.853116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.8572272609252483934997356779481416714479051013849207726740677170495912541258
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2923.865000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2923.865000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.64137552496366159924976531265300665677761690705186400366831499715665820561409
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2859.936000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2859.936000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.60870827736931160144252817792379675065963009872240725816071107053066893957477
    Line 444, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 18128.601817 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 18128.601817 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.56150450911742851995447868335530761752183224895484368433901070600857832384889
    Line 667, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.58507047752549781368070276500440066483547742158560554943182212226830415780124
    Line 784, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@217829) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.30765517248758826285827872608238045450794457249683829958681527638394516557973
Line 244, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 7715.733712 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@217829) { a_addr: 'h106ac  a_data: 'h2c650bc6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1aea6  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 7715.733712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---