ADC_CTRL Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.160s	5.938ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.720s	1.543ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.780s	569.097us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	9.750s	27.277ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.290s	783.147us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.780s	408.191us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.780s	569.097us	1	1	100.00
		adc_ctrl_csr_aliasing	2.290s	783.147us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	8.912m	338.404ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.406m	160.990ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.231m	159.096ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	7.951m	327.209ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	15.845m	551.315ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.628m	380.976ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	9.630m	352.082ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	6.320s	15.016ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.570s	3.250ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	16.110s	35.081ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.104m	119.948ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	1.174m	72.280ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.340s	411.216us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.110s	312.084us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.000s	451.690us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.000s	451.690us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.720s	1.543ms	1	1	100.00
		adc_ctrl_csr_rw	1.780s	569.097us	1	1	100.00
		adc_ctrl_csr_aliasing	2.290s	783.147us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.940s	4.022ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.720s	1.543ms	1	1	100.00
		adc_ctrl_csr_rw	1.780s	569.097us	1	1	100.00
		adc_ctrl_csr_aliasing	2.290s	783.147us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.940s	4.022ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	16.630s	8.537ms	1	1	100.00
		adc_ctrl_tl_intg_err	8.980s	4.549ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	8.980s	4.549ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.530s	27.149ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.7926417771878475504781696572258781667844294766354311667362304248480366263430
      Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 15015954568 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 15015954568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---